Sony DVP-CX995V Service Manual page 80

DVP-CX995V
Pin No. Pin Name
DAC-PCMOUT0 to
52 to 54
DAC-PCMOUT2
55 DAC-PCMCLK
56 DAC-LRCLK
57 SPDIF-OUT
SMI-ADR (4) to
58 to 63
SMI-ADR (9)
64 VDD1-8
65 VSS
SMI-ADR (3) to
66 to 69
SMI-ADR (0)
SMI-ADR (10) to
70 to 73
SMI-ADR (13)
74
SMI-CS (0)
75
SMI-CS (1)
76
SMI-RAS
77
SMI-CAS
78
SMI-WE
79
SMI-DQML
80
SMI-DQMU
81 VDD3-3
82 SMI-CLKIN
83 VSS
SMI-DATA (0) to
84 to 93
SMI-DATA (9)
94 VDD1-8
95
SMI-CLKOUT
96 VSS
SMI-DATA (10) to
97 to 102
SMI-DATA (15)
103 TMODE_SW
104 +5V_CONT_B
105 ADY_CS
106 ADC-PCMCLK
107 VDD3-3
108 VSS
109 TRST
110 TMS
111 TDO
112 TDI
113 TCK
114 ADY_BYPASS
115 BOOT_MODE
116 WP
117
CPU-OE
118
CPU-PROCLK
119 VDD1-8
120 PIX-CLK
80
I/O
O
PCM audio data output to the D/A converter
O
Master clock signal output to the SACD media player, D/A converter and HDMI transmitter
O L/R sampling clock signal output to the D/A converter
O
SPDIF signal output to the digital out jack and HDMI transmitter
O
Address signal output to the SD-RAM
-
Power supply terminal (+1.8V)
- Ground terminal
O
Address signal output to the SD-RAM
O
Address signal output to the SD-RAM
O
Chip select signal output to the SD-RAM
O
Chip select signal output terminal Not used
O
Row address signal output to the SD-RAM
O
Column address signal output to the SD-RAM
O
Write enable signal output to the SD-RAM
O
Write mask signal output to the SD-RAM (lower byte)
O
Write mask signal output to the SD-RAM (upper byte)
-
Power supply terminal (+3.3V)
I
133 MHz clock signal input terminal
-
Ground terminal
I/O
Two-way data bus with the SD-RAM
- Power supply terminal (+1.8V)
O
133 MHz clock signal output to the SD-RAM
-
Ground terminal
I/O
Two-way data bus with the SD-RAM
I
Test mode on/off control signal input from the system controller "H": test mode on
O Power on/off control signal output terminal for HDMI section (+5V) Not used
O
Chip select signal output terminal Not used
O
PCM clock signal output terminal Not used
-
Power supply terminal (+3.3V)
- Ground terminal
I Reset signal input terminal (for JTAG)
I Mode selection signal input terminal (for JTAG)
O Data output terminal (for JTAG)
I Data input terminal (for JTAG)
I Clock signal input terminal (for JTAG)
O
Bypass signal output terminal Not used
O
Boot mode selection signal output terminal Not used
O Write protect signal output terminal Not used
O
Output enable signal output to the flash memories
O
Not used
-
Power supply terminal (+1.8V)
I 27 MHz clock signal input terminal
Description