Mitsubishi DS907x SIP User Manual page 92

USER'S GUIDE
INTERRUPT ENABLE CONTROL BITS Figure 11–2
Bit Description:
All bits are read/write at any time and are cleared to 0 following any hardware reset.
IE.7:
"Enable All Interrupts":
IE.4:
"Enable Serial Interrupt":
IE.3:
"Enable Timer 1 Interrupt":
IE.2:
"Enable External
Interrupt 1":
IE.1:
"Enable Timer 0 Interrupt":
IE.0:
"Enable External
Interrupt 0":
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EA
When set to 1, each interrupt except for PFW may be individually enabled or
disabled by setting or clearing the associated IE.x bit. When cleared to 0,
interrupts are globally disabled and no pending interrupt request will be ac-
knowledged except for PFW.
ES
When set to 1, an interrupt request from either the serial port's TI or RI flags
can be acknowledged. Serial I/O interrupts are disabled when cleared to 0.
ET1
When set to 1, an interrupt request from Timer 1's TF1 flag can be acknowl-
edged. Interrupts are disabled from this source when cleared to 0.
EX1
When set to 1, an interrupt from the IE1 flag can be acknowledged. Inter-
rupts are disabled from this source when cleared to 0.
ET0
When set to 1, an interrupt request from Timer 0's TF0 flag can be acknowl-
edged. Interrupts are disabled from this source when cleared to 0.
EX0
When set to 1, an interrupt request from the IE0 flag can be acknowledged.
Interrupts are disabled from this source when cleared to 0.
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