Section 10 Reset Conditions - Mitsubishi DS907x SIP User Manual

USER'S GUIDE
SECTION 10: RESET CONDITIONS
Reset Sources
The Secure Microcontroller family is designed to pro-
vide proper reset operation with a minimum of external
circuitry. In fact, for may applications, external reset cir-
cuitry is not required. The possible sources of reset are
as follows:
a) Power On (operating voltage applied to V
b) No V Power On
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c) External RST pin
d) Watchdog Timeout
RESET STATUS BITS Figure 10–1
PCON.6:
"Power On Reset":
Initialization:
Read Access:
Write Access:
PCON.4:
"Watchdog Timer Reset":
Initialization:
Read Access:
Write Access:
PCON.2:
"Enable Watchdog Timer":
Initialization:
Read Access:
Write Access:
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CC
POR
Indicates that the previous reset was initiated during a Power On.
Cleared to a 0 whenever a Power On Reset occurs; remains unchanged on
other types of resets. Must be set to a 1 by software.
Can be read normally anytime.
Can be written only by using the Timed Access register.
WTR
Set to a 1 when a timeout condition of the Watchdog Timer occurs. Cleared
to a 0 immediately following a read operation.
Set to a 1 on a Watchdog Timeout Reset. Remains unchanged on any other
type of reset.
Read normally anytime.
Not writable.
EWT
The Watchdog Timer is enabled if EWT is set to a 1 and is disabled if EWT is
cleared to a 0. This is not normally considered a status bit but is convenient
for detecting a No V reset condition.
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Cleared to a 0 on a No–V
other types of reset.
May be read normally anytime.
Writable only by using the Timer Access register.
Certain actions are taken in all cases where a reset has
been issued. Whenever any type of reset is executed,
the ALE and PSEN quasi–bidirectional pins are confi-
gured as inputs. In addition, an internal reset line (IRST)
is active continuously until the condition which is caus-
ing the reset has been removed. IRST will then go inac-
tive and execution of the application program will begin.
Special Function Registers are initialized during reset
as shown in Table 10–1.
Figure 10–1 is a summary of the bits that indicate the
source of the most recent reset. Operational details
which are unique to the different sources of reset are
discussed below:
Power On Reset. Remains unchanged during
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