Section 11 Interrupts - Mitsubishi DS907x SIP User Manual

SECTION 11: INTERRUPTS
The Secure Microcontroller family follows the standard
8051 convention for interrupts (with one extra) and is
fully compatible. An interrupt stops the normal flow of
processing and allows software to react to an event with
special processing. This event can be external, time–re-
lated, or the result of serial communication. However,
the interrupt will not be performed until the completion of
the current instruction. This is discussed in more detail
below. For each interrupt, there is an interrupt vector
location. When an interrupt occurs, the CPU effectively
performs a call to the corresponding vector address.
The interrupt vector is the location of the Interrupt Ser-
vice Routine (ISR). Since the vector addresses are
closely spaced, these ISRs typically use a jump to
another more convenient location. An ISR performs
special processing associated with the event that
caused the interrupt. When the ISR is complete, the
user returns control to the main program using an RETI
instruction. This is the last instruction in an ISR and it
performs two functions. First, it returns control to the
instruction in the main program preempted by the inter-
rupt. Second, the RETI clears the pending interrupt
INTERRUPT SOURCE
External Interrupt 0
Timer Interrupt 0
External Interrupt 1
Timer Interrupt 1
Serial I/O
Power Fail Warning
INTERRUPT SOURCES
As shown above, there are two External Interrupts, two
Timer Interrupts, two Serial Communication Interrupts,
and a Power–fail Interrupt. To use an interrupt (except
PFW), the software must globally enable the interrupt
function. This is done with the EA bit (IE.7). Setting this
INTERRUPT SOURCE
External Interrupt 0
Timer Interrupt 0
External Interrupt 1
Timer Interrupt 1
Serial Port Interrupt
Power Fail Interrupt
condition. This allows the CPU to respond to other inter-
rupts.
Each interrupt generally has an enable–control bit, a
status flag bit, and a priority bit. Except for the new Pow-
er–fail Interrupt, the enable–control bits are located in
the IE register and the priority bits are located in the IP
register. The flags are scattered. Each interrupt aspect
is discussed below.
There are six interrupt vector locations in a Secure
Microcontroller. Generally each interrupt has an
associated vector location and flag. In the case of the
Serial Interrupt, there are two sources with the same
vector, but a separate flag indicates the source of the
event. Each ISR vector has a unique physical address .
For example, the External interrupt 0 vector is location
0003h, but the Timer 0 vector is 000Bh. Also note, the
flags correspond to the event, not the interrupt. These
flags will be activated even if a particular interrupt is not
enabled so that software can poll the event. The flags
(except serial port) are cleared when the CPU calls to
the interrupt vector.
VECTOR ADDRESS
0003h
000Bh
0013h
001Bh
0023h
002Bh
bit to a logic 1 turns on the interrupt function. EA is
cleared to a logic 0 by all resets. Next, each individual
interrupt must be enabled. This is done using the other
bits of the Interrupt Enable (IE) SFR. Each source has a
corresponding bit that must be set to a logic 1. These are
listed below.
ENABLE BIT
EX0
ET0
EX1
ET1
ES
EPFW
89
FLAG FLAG LOCATION
IE0 TCON.1
TF0 TCON.5
IE1 TCON.3
TF1 TCON.7
RI & TI SCON.0, SCON.1
PFW PCON.5
LOCATION
IE.0
IE.1
IE.2
IE.3
IE.4
PCON.3
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