Denon S-102 Service Manual page 47

Name Pin Numbers
TSD0
33
SEL_PLL0
TSD1
36
SEL_PLL1
TSD2 37
TSD3 38
MCLK 39
TBCK 40
SEL_PLL3
41
SPDIF_OUT
SPDIF_IN 42
RSD 45
RWS 46
RBCK 47
CAMIN3
48
PIXIN3
XIN 49
XOUT 50
AVEE 51
AVSS 52
DMA[11:0] 53-58, 61-66
DCAS# 69
DOE#
70
DSCK_EN
DWE# 71
DRAS# 72
DMBS0 73
DMBS1 74
DB[15:0] 77-82, 85-90, 93-96
DCS[1:0]# 97,100
DQM 101
DSCK 102
I/O Definition
O Audio transmit serial data output 0.
I Refer to the description and matrix for SEL_PLL2 pin 32.
O Audio transmit serial data output 1.
I Refer to the description and matrix for SEL_PLL2 pin 32.
O Audio transmit serial data output 2. This pin must be pulled down to VSS via a
4.7-k resistor for proper operation.
O Audio transmit serial data output 3.
I/O Audio master clock for audio DAC.
I/O Audio transmit bit clock. TBCK is an input during reset and subsequently is
programmed as an output via the AUDIOXMT register (addr 0x2000D00Ch, bit 4).
I Clock source select. Strapped to VCC or ground via 4.7-k
during reset.
SEL_PLL3
0 Crystal oscillator
1 DCLK input
O S/PDIF output.
I S/PDIF input; (5V tolerant input).
I Audio receive serial data; (5V tolerant input).
I Audio receive frame sync; (5V tolerant input).
I Audio receive bit clock; (5V tolerant input).
I Camera YUV 3.
I CCIR656 input pixel 3.
I 27-MHz crystal input.
O 27-MHz crystal output.
P Analog power for PLL.
G Analog ground for PLL.
O DRAM address bus.
O DRAM column address strobe.
O DRAM output enable.
O DRAM clock enable.
O DRAM write enable.
O DRAM row address strobe.
O DRAM bank select 0.
O DRAM bank select 1.
I/O DRAM data bus.
O DRAM chip select.
O Data input/output mask.
O Output clock to DRAM.
47
Clock Source
S-102
resistor; read only