Denon S-102 Service Manual page 48

Name Pin Numbers
DCLK 105
UDAC
106
YUV0
PIXOUT0
VREF
YUV1 107
PIXOUT1
CDAC
YUV2 108
PIXOUT2
COMP
YUV3 109
PIXOUT3
RSET
YUV4 110
PIXOUT4
I/O Definition
I Clock input to PLL; (5V tolerant input).
O Video DAC output.
F DAC
Value
(pin 115)
0 CVBS/Chroma
1 CVBS/Chroma
2 CVBS/Chroma
3 CVBS/Chroma
4 CVBS/Chroma
5 CVBS/Chroma
6 CVBS/Chroma
7 N/A
8 CVBS/Chroma
9 CVBS
10 CVBS
11 N/A
12 CVBS/Chroma
13 CVBS/Chroma
14 Chroma
F: CVBS/chroma signal for simultaneous mode.
Y: Luma component for YUV and Y/C processing.
C: Chrominance signal for Y/C processing.
U: Chrominance component signal for YUV mode.
V: Chrominance component signal for YUV mode.
O YUV pixel 0 output data.
O CCIR656 output pixel 0.
I Internal voltage reference to video DAC. Bypass to ground with 0.1- F capacitor.
O YUV pixel 1 output data.
O CCIR656 output pixel 1.
O Video DAC output. Refer to description and matrix for UDAC pin 106.
O YUV pixel 2 output data.
O CCIR656 output pixel 2.
I Compensation input. Bypass to ADVEE with 0.1- F capacitor.
O YUV pixel 3 output data.
O CCIR656 output pixel 3.
I DAC current adjustment resistor input.
O YUV pixel 4 output data.
O CCIR656 output pixel 4.
48
V DAC Y DAC C DAC
(pin 114) (pin 113) (pin 108)
CVBS1 Y C
CVBS1 Y C
N/A Y C
CVBS1 N/A N/A
CVBS1 N/A N/A
CVBS1 Y Pb
N/A Y Pb
SYNC G B
Chroma Y Pb
CVBS1 G B
CVBS1 G R
SYNC G R
N/A Y Pr
CVBS1 Y Pr
Y G R
S-102
U DAC
(pin 106)
N/A
CVBS2
N/A
CVBS2
N/A
Pr
Pr
R
Pr
R
B
B
Pb
Pb
B