Sharp LC-32WD1E/S/RU Service Manual page 73

LC-32WD1E/S/RU, LC-37WD1E/S/RU, LC-42WD1E/S/RU, and LC-32/37/42WT1E
Ref No. Name
D040 PNX processor
D050 DDR memory
D051 DDR memory
D052 Flash memory
D080 CPLD
Part Code Description
PNX5010E The PNX1500 Media Processor Series is a complete Audio/
Video/Graphics system on a chip that contains a high-
performance 32-bit VLIW processor, TriMediaä TM3260,
capable of high quality software video (multi-video standard
digital decoder/ encoder and image improvement), audio signal
processing, as well as general purpose control processing. It
can either be used in standalone, or as an accelerator to a
general purpose processor. The PNX1500 processes the input
signals by utilizing several Audio/Video and co-processor
modules before send them to the external peripherals. These
modules provide additional video and data processing
bandwidth without taking away precious CPU cycles. The
combination of the CPU and co-processor modules makes the
PNX1500 System On-Chip (SoC) suitable for most
applications, especially those requiring high level of processing
power/ throughput at a reduced cost.
K4H561638F-UCC The K4H280438E / K4H280838E / K4H281638E is
134,217,728 bits of double data rate synchronous DRAM
organized as 4x 8,388,608 / 4x 4,194,304 / 4x 2,097,152 words
by 4/ 8/16bits, fabricated with SAMSUNG's high performance
CMOS technology. Synchronous features with Data Strobe
allow extremely high performance up to 333Mb/s per pin. I/O
K4H561638F-UCC
transactions are possible on both edges of DQS.
Range of operating frequencies, programmable burst length
and programmable latencies allow the device to be useful for a
variety of high performance memory system applications.
KFG5616U1A-PIB OneNAND™ is a monolithic integrated circuit with a NAND
Flash array using a NOR Flash interface.
This device includes control logic, a NAND Flash array, and
3KB of internal BufferRAM.
The BufferRAM reserves 1KB for boot code buffering
(BootRAM) and 2KB for data buffering (DataRAM), split
between 2 independent buffers. It has a x16 Host Interface and
a random access time speed of ~76ns.
The device operates up to a maximum host-driven clock
frequency of 54/66MHz for synchronous reads at Vcc (or
Vccq.) with minimum 4-clock latency. Below 40MHz it is
accessible with minimum 3-clock latency.
Appropriate wait cycles are determined by programmable read
latency.
OneNAND™ provides for multiple sector read operations by
assigning the number of sectors to be read in the sector
counter register. The device includes one block-sized OTP
(One Time Programmable) area that can be used to increase
system security or to provide identification capabilities.
XC2C128-7TQG14 Xilinx CoolRunner™-II CPLDs deliver the high speed and ease
of use associated with the XC9500/XL/XV CPLD family with the
extremely low power versatility of the XPLA3™ family in a
single CPLD. This means that the exact same parts can be
used for high-speed data communications/
computing systems and leading edge portable products, with
the added benefit of In System Programming. Low power
consumption and high-speed operation are combined into a
single family that is easy to use and cost effective. Clocking
techniques and other power saving features
extend the users' power budget. The design features are
supported starting with Xilinx ISE 4.1i ISE WebPACK.
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