1
QQ
• Pin Function
3 7 63 1515 0
Pin No.
Pin Name
A
3
HD1-IN
1
HD2-IN
11
HD3-IN
4
VD1-IN
2
VD2-IN
10
VD3-IN
5
ANALOG GND
6
AFC FILTER
7
HVCO
8
VCC
20
DAC1
(V. SYNC output)
B
9
DAC2
(H/C. SYNC output)
24
DAC3
12
CP-OUT
13
HD1-OUT
15
HD2-OUT
14
DIGITAL GND
16
SDA
17
SCL
18
ADDRESS SW
21
SYNC1-IN
19
SYNC2-IN
C
22
VD1-OUT
23
VD2-OUT
TE
L 13942296513
D
E
www
F
126
1
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2
I/O
I
Input the horizontal synchronizing signal.
I
It's polarity corresponds to both positive and negative.
I
Input from this pin does not be synchronized internally.
I
Input the horizontal vertical signal.
I
It's polarity corresponds to both positive and negative.
I
Input from this pin does not be synchronized internally.
—
The GND pin for analog circuit block.
—
Connect the filter for horizontal AFC. The frequency of the horizontal output is varied
by the volyage at this pin.
—
Connect the ceramic oscillator for horizontal oscillator.
—
The VCC pin. (9.0V)
O
DAC1 output pin. When TEST mode, VD or vertical sync signal to frequency counter
circuit is output.
O
DAC2 output pin. When TEST mode, HD or composite sync signal to frequency
counter circuit is output.
O
DAC3 output pin. This pin is open-collector system. When TEST mode, test pilses for
the shipping is output.
O
Clamp pulse output pin. CP mode at synchronization circuit is output.
O
HD output pin. This pin is open-collector system.
O
HD1/HD2 does not be synchronizing and they are output from this pin.
It's polarity is switched by BUS write function.
—
The GND pin for logic circuit block.
I/O
The SDA pin for I"C BUS.
I
The SCL pin for I"C BUS.
I
Slave address switch.
I
Input a signal to separate sync signal.
I
O
VD output pin. This pin is open-collector system.
O
VD1/VD2 does not be synchronizing and they are output from this pin.
It's polarity is switched by BUS write function.
x
ao
y
.
i
PDP-R03U
2
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3
8
Pin Function
Q Q
3
6 7
1 3
u163
.
3
4
2 9
9 4
2 8
1 5
0 5
8
2 9
9 4
m
co
4
9 9
2 8
9 9