Table of Contents
Advertisement
Circuit Description
The Direction line comes in on Pin 34 of the interface connector. A high signal directs the step logic to
step toward Track 00. A low signal directs the step logic to step toward a higher numbered track.
The direction line sets the proper phase to the exclusive OR gates of U9.
Step Out Toward Track 00
Pin No.
0
U21-9
0
U21-8
1
U21-5
0
U21-6
1
The step pulses come in at Pin 36 of the interface connector. They are buffered by U22 and gated at
U14 by the unit select, and the Not Write signal. The step pulses then go to the C inputs of the two flip
flops at U21. The direction of the step, hence the selection of the flip flop to be toggled, is done by the
two exclusive OR gates of U9. These gates are controlled by the step direction line and by the state of
the two flip flop outputs.
The POR- (Power On Reset) signal resets the two flip' flops to Phase 0 after a Power On.
The output of the two flip flops drives the stepper motor through the drivers of U39, U40, and U12. The
diodes, CR2-9, are for voltage spike elimination. The current through the st e p per motor coils is
reversed sequentially, one at a time.
D. WAX"GITE
Functional Description
When the Write Gate signal is true (low), the write electronics are prepared for writing data (read
electronics disabled). This signal turns on the write current in the read/write head. Data is written
under control of the Write Data input line. It is necessary for the Write Gate interface line to go low
before the first Write Data pulse. However, the separation between the leading edge of Write Gate
and the first significant Write Data pulse should not be less than two microseconds and not greater
than four microseconds. The same restrictions exist for the relationship between the last Write Data
pulse and the termination of the Write Gate signal. When the Write Gate line goes false (high), the
trim erase will stay on for 550 microseconds (see Trim Erase, page 3-7).
When a w r i t e-protected d i s kette i s i n s t a lled i n t h e d r i ve, th e w r it e e l e c t ronics ar e d i s a bled,
irrespective of the s t ate of th e W r ite Gate l ine. Check the l ist of o p t ions (see Section 1.19) for
exceptions and further discussion of write protect options. Stepping is also disabled by a true (low)
Write Gate.
Tendon Corporation recommends that the controller wait one millisecond after the WWRWATE goes
high (false) before any step pulses are sent to the drive.
C ircuit Descri t i o n
A low (true) WRT GATE signal is applied to Pin 40 of th e i n terface connector P13. This signal is
TABLE 3-2
STEPPER LOGIC TRUTH TABLE
Phase
3
2
1
0
1
1
0
0
0
0
1
1
0
1
1
0
1
0
0
1
3-5
Step In Toward The
Pin No.
0
1
U21-9
0
0
U21-8
1
1
U21-5
0
1
U21-6
1
0
Upper Tracks
Phase
2
3
0
1
1
0
0
0
1
1
0
0
0
1
1
Advertisement
Table of Contents
