Instructions Of Command Sets; Ieee 488.2 Common Commands - Escort 3136A Operation Manual

Standard Event Status Enable Register (ESE)
The Standard Event Status Enable Register is a mask register that allows the host
to enable or disable (mask) each bit in ESR. When a bit in the ESE is 1, the
corresponding bit in the ESR is enabled. When any enabled bit in the ESR changes
from 0 to 1, the ESB summary bit (bit 5) of the STB register also goes to 1.
Use "*ESE" to write to this register and "*ESE?" to read this register.

7-5 Instructions of Command Sets

7-5-1 IEEE 488.2 Common Commands

*CLS
Description: Clear the Standard Event Status Register and System Error Queue.
*ESE <NRf>
Description: Set the Standard Event Status Enable Register.
Parameter: <NRf> (0 to 255).
Example: *ESE 140
Enable bits 2 (QYE), 3 (DDE), and 7 (PON), and disable all the other bits.
*ESE?
Description: Query the Standard Event Status Enable Register.
Response: (Integer) Decimal equivalent of the register byte. Range is 0 to 255.
*ESR?
Description: Query the Standard Event Status Enable Register and clears the register.
Response: (Integer) Decimal equivalent of the register byte.
Example: *ESR?
Return '32'if bit 5 (CME) is set (1) and the rest of the bits are reset (0).
*IDN?
Description: Query the Meter identification.
Response: Return Model number and Firmware version.
*OPC
Set the Operation Completed bit in the Standard Event Status Register
Description:
when all pending device operations are completed.
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