Ccd Drive Clock Generator Circuit - Panasonic DF-1100 Service Manual

6.2.4 CCD Drive Clock Generator Circuit

This circuit is also contained in IC9. Its function is to generate FSG, FCK1 and FR1 clock signals, which are
required for driving the CCD. These clock signals are generated by the system clock generator circuit derived
from the 25.0 MHz clock signal that is input to IC90. Its timing chart is shown below.
The FSG, F1CK, F2CK, FR1 and FR2 clock supplied to the CCD is output from the OFSG, OFCK1, OFCK2,
RS1 and CP1 of IC40 (DZZAC000097). These clocks of IC40 are derived from the FSG, FCK1, and FR1
clock of IC90 (MN86072) generates the timing of the FSG, F1CK, F2CK, FR1 and FR2 clock to drive the
CCD.
FSG
F1CK
F2CK
FR1
FR2
CCD
uPD3739D
TG
CK1
CK1
CK1L
CK2
CK2
CK2L
R1
R2
FSG OFSG
F1CK OFCK1
CCD
Drive
F2CK OFCK2
Circuit
FR1 RS1
IC40
FR2 CP1
DZZAC000097
System Description
FSG
FCK1
IC90
FR1
MN86072
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