Logic Circuits - Icom IC-756PRO III Service Manual

3-6-3 MAIN-A UNIT
LINE
Receive 8 V converted from the 14 V line and
R8V regulated by the R8V regulator circuit (Q601,
Q602, D601).
Transmit 8 V converted from the 14 V line and
T8V regulated by the T8V regulator circuit (Q611,
Q612, D611).
3-6-4 CTRL-A AND PLL UNITS
LINE
Common 5 V for the antenna tuner CPU
(CTRL-A unit; IC5), EEPROM (CTRL-A unit;
5V IC6) and etc. converted from the 14 V line and
regulated by the +5 regulator circuit (CTRL-A
unit; IC13).
Common 5 V for each PLL-A and PLL-B circuits
regulated from the 8 V line and regulated by
5V
the +5 regulator circuit (PLL unit; IC382: PLL-A,
IC682: PLL-B).

3-7 LOGIC CIRCUITS

3-7-1 BAND SELECTION DATA
(RF-B, CTRL-A, PLL UNITS)
Frequency IC401–IC403
[MHz] (RF-B )
0.03–1.5999999 B0
1.6–1.999999 B1
2.0–2.999999 B2
3.0–3.999999 B3
4.0–4.999999
B4
5.0–5.999999
6.0–6.999999 B5W
7.0–7.299999 B5
7.3–7.999999 B5W
8.0–10.999999 B6
11.0–11.999999
B7W
12.0–13.999999
14.0–14.499999 B7
14.5–14.999999 B7W
15.0–19.999999
B8W
20.0–20.999999
21.0–21.499999 B8
21.5–21.999999 B8W
22.0–29.999999 B9
30.0–44.999999
B10W
45.0–49.999999
50.0–54.000000 B10
54.0–60.000000 B10W
DESCRIPTION
DESCRIPTION
IC11 IC101 IC401
(CTRL-A) (PLL) (PLL)
L1S
L2S
VA1S VB1S
L3S
L4S
VA2S VB2S
L5S
L6S
VA3S VB3S
L7S
L8S
VA4S VB4S
3-7-2 SUB-CPU PORT ALLOCATIONS
(DISPLAY BOARD; IC401)
Pin Port
number name
OSC1,
7, 8
OSC2
DRES
9
MSB,
12, 83
MSA
DOTK,
56, 57
DSHK
MDM0–
64–66
MDM2
TNRD, MOND
NBD, NRD
LOCD, TXD
67–75
RXD, PBTD
NOTD
PB1B,
77, 79
PB1A
METV
81
RSA,
82, 84
RSB
PB2A,
85, 88
PB2B
LMFD
86
LFMD
87
BALL
92
NRL
93
MIGL
94
PWRL
95
CMPL
96
KYSL
97
DELL
98
NOTL
99
PITL
100
3 - 10
Description
Input and output ports for the system
clock oscillator (X401; 9.8304 MHz).
Input port for the reset signal.
Input port for the [DIAL]; pulse-type
signals are applied.
Input ports for the [ELEC-KEY] jack.
Output ports for the S/RF meter back-
light and function switch activation
indicator brightness control signal.
Backlight level
Port
1 2 3 4
High Low High Low High
MDM0
Low High High Low Low
MDM1
Low Low Low High High High High
MDM2
Control signal output ports for the
activation indicator of function switch-
es.
High : When the function is activated.
Input port for the [TWIN PBT (inner)]
control (PBT board, S1/inner).
Outputs the S/RF meter (ME1) drive
signal.
Input ports for the [RIT/∆TX] control;
pulse-type signals are applied.
Input port for the [TWIN PBT(outer)]
control (PBT board, S1/outer).
Input port for data signal from the
main-CPU (MAIN-A unit; IC3501).
Outputs data signal for the main-CPU
(MAIN-A unit; IC3501).
A/D input port for the [BAL] control
(R702/ inner).
A/D input port for the [NR] control
(R702/ outer).
A/D input port for the [MIC GAIN]
control (R712).
Input port for the [RF POWER] con-
trol (R714).
Input port for the [COMP] control
(R716).
Input port for the [KEY SPEED] con-
trol (R718).
Input port for the [BK-IN DELAY] con-
trol (R720).
Input port for the [NOTCH] control
(PBT board, R1/inner).
Input port for the [CW PITCH] control
(PBT board, R1/outer).
5 6 7
Low High
High High