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Tavll = 68 ns MIN.
Tavll(AO-A15) = 5 ns (AC373 Ts MIN).
TavIl(WAIT) = 11 ns (AC373 Dn to On Tplh MAX) + 35 ns (PAUEPLD
Tpd MAX)
+ 8 ns (AC00 Tphl MIN) + 5 ns (AC1 12 Tw MIN)
= 59 ns.
TavII(BHE#) = 11 ns (AC14 Tplh MAX) + 4 ns (AC1 12 Tsu MIN)
= 15 ns.
Tllax = 43 ns MIN.
Tllax(A,O-A15) = 0 ns (AC373 Th MIN).
Tllax(BHE#) = 0 ns (AC1 12 Th MIN).
Tllrl = 43 ns MIN.
Tllrl(UART) = 7 ns (UART Tavrl MIN).
Trlcl is irrelevant in this design.
Trlrh = 411 ns MIN, for two wait states.
Trlrh(UART) = 281 ns (UART Trlrh MIN).
Trhlh = 83 ns MIN.
Trhlh(STALE)
= 9 ns (74AC08 Tplh MAX) + 3 ns (74AC112 Trem MIN)
=12ns.
Tllwl = 73 ns MIN.
Tllwl(UART) = 7 ns (UART Tavwl MIN).
Tclwl is irrelevant in this design.
Tqvwh = 60 ns MIN, for zero wait states.
Tqvwh(ROMsim)
= 40 ns (RAM Tdw MIN).
Tqvwh = 393 ns MIN, for two wait states.
Tqvwh(UART)
= 90 ns (UART Tdvwh MIN).
Tchwh is irrelevant in this design.
Twlwh = 53 ns MIN, for zero wait states.
Twlwh(ROMsim)
= 50 ns (RAM Twp MIN).
Twlwh = 386 ns MIN, for two wait states.
Twlwh(UART)
= 231 ns (UART Twlwh MIN).
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