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Timing analysis of the EV80C196KB board.
All values used are based on the 8OCl96KB
operating at 12MHz. They
are taken from the October 1988 version of the 8OCl96KB
data sheet,
Intel order number 270634-001.
8OC196KB AX. Characteristics
Tavyv = 81 ns MAX.
Tavyv(WAIT) = 11 ns (AC373 Dn to On Tplh MAX) + 35 ns (PAUEPLD Tpd MAX)
+ 9 ns (AC08 Tplh MAX) + 12 ns (AC112 RES to Q Tphl MAX)
= 67 ns.
Tllyv is irrelevant in this design.
Tclyx = 53 ns MAX.
Tclyx(WAIT) = 10 ns (AC11 2 CLOCK to Q Tplh MAX).
Tllyx is irrelevant in this design.
Tavgv = 81 ns MAX.
Tclyx(BUSWIDTH)
= 11 ns (AC373 Dn to On Tplh MAX) + 35 ns (PAUEPLD Tpd
MAX)
= 46 ns.
Tllgv is irrelevant in this design.
Tclgx is irrelevant in this design.
Tavdv = 183 ns MAX, for zero wait states.
Tavdv(ROMsim)
= 11 ns (AC373 Dn to On Tplh MAX) + 35 ns (PAUEPLD Tpd
MAX)
+ 100 ns (RAM Tcol MAX)
= 146 ns.
Tavdv = 349 ns MAX, for one wait state.
Tavdv(EPROM)
= 11 ns (AC373 Dn to On Tplh MAX) + 35 ns (PAUEPLD Tpd MAX)
+ 200 ns (EPROM Tee MAX)
= 246 ns.
Tavdv = 516 ns MAX, for two wait states.
Tavdv(UART)
= 11 ns (AC373 Dn to On Tplh MAX) + 35 ns (PAUEPLD Tpd MAX)
+ 288 ns (UART Tavrl MIN + Trldv MAX)
= 334 ns.
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