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Preliminary
10.2 8.2.
PCI Address
The PCI address register is a 30 bit counter loaded from bits D31:2 of the C40 data bus. The counter
output is a 32 bit address with bits 1:0 always at logic 0.
The PCI Address register must be written with a valid PCI address prior to writing or reading from the
FIFO. The value written into the address register loses the bottom two bits in order to match the PCI bus
mode used by the bridge. The address counter increments on every valid PCI to track the source or
destination pointer in the event of a target disconnect. The bridge may disconnect during burst transfers
but this will be transparent to the C40.
10.3 8.3.
C40 Control Register
The Control register provides the C40 interface with control over the generation of interrupts on the PCI
bus. Writing a 1 to the PCI INT bit will generate an interrupt on the PCI bus via the INTA line. The interrupt
is cleared / acknowledged through the target interrupt control register.
Document Name:
User Guide
Product Name:
SMT327
Author:
Bill Blyth
Page 20 of 20
Bit(s)
31-24
23:16
Name
0
0
15:2
1
0
PCI INT
Issue : 01
Revision Date:
Original Date:
SMT327 User Guide
0
BURST
Rev 02
8 August, 2000
30 April 1998
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