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Preliminary
7. JTAG Input & Output Ports
Both input and output ports for JTAG are provided, designed to be compatible with the SMT328 and
SMT301 motherboards.
The JTAG interface is designed to operate at a maximum 10MHz across up to 4 SMT327 motherboards.
By default this frequency is 8.33MHz (PCI_CLK/4) or less, depending on the PCI_CLK on the host.
The JTAG ports of the SMT327 auto-detect connections and will by default become a JTAG master with
no connections or with a slave SMT327 connected to the JTAG-OUT port. An SMT327 that detects a
cable connection on its JTAG-IN port automatically becomes a slave and routes the TAP port accordingly.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Document Name:
User Guide
Product Name:
SMT327
Author:
Bill Blyth
Signal
Direction
TDI
IN
GND
TDO
OUT
GND
TMS
IN
GND
TCK
IN
GND
TCK_RET
OUT
GND
-TRST
IN
GND
-RESET
IN
PD
OUT
-DETECT
IN
CONFIG
OPEN COLL
EMU0
OUT
EMU1
OUT
SPARE1
SPARE2
Table 2 JTAG Slave Port (Input)
Description
JTAG data in
JTAG data out
JTAG Test mode select
JTAG clock, up to 10MHz
JTAG clock return
JTAG Reset
Board Reset in
Presence detect, +5V 1A
fused
Detect external JTAG
controller when grounded
Global open collector C4x
CONFIG
Buffered EMU0 output
Buffered EMU1 output
Issue : 01
Revision Date:
Original Date:
Rev 02
8 August, 2000
30 April 1998
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