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Preliminary
10. Bridge - C40 Operation.
The first TIM position on the SMT327 makes use of the global bus to allow the C40 to read and write the
entire PCI address space. Burst mode and single transfers can be used to access the PCI address
space.
C40
Data
Add
The C40 can access any PCI location but in should be noted that data written and read will always be
long word aligned and 32 bits wide. The table below illustrates the available registers.
Address
C0000000
C0400000
C0800000
10.1 8.1.
FIFO
The SMT327incorporates 16 deep x 32 wide FIFO buffers on both read and write paths between the C40
and PCI bus. The FIFO is only effective when burst mode is enabled in the control register. With burst
mode disabled, the bridge will request the PCI bus for each word transferred.
With burst mode enabled, data written to the empty FIFO will be absorbed until 16 words make the FIFO
full. This state will trigger a PCI burst write of 16 words in length thus transferring 64 bytes to the
destination. The FIFO can be written with the next 16 words during the PCI burst transaction to maintain
throughput. The C40 may incur wait states if the FIFO becomes full during this time.
For burst mode read transactions, reading from the empty FIFO will trigger a PCI burst of 16 words from
source memory, filling the FIFO with 64 bytes of data. The C40 will be able to read the first word of data
as soon as it is loaded into the FIFO from the PCI bus.
Document Name:
User Guide
Product Name:
SMT327
Author:
Bill Blyth
Page 19 of 19
32 bit
Add
Ctrl
FIFO
16 x32
FIFO
16 x32
Decoder
Figure 4 Master Mode Interface
Register(Write)
FIFO
PCI Address
Control
Register(Read)
FIFO
-
-
Issue : 01
Revision Date:
Original Date:
SMT327 User Guide
PCI
ADIO
Width
32
32
2
Rev 02
8 August, 2000
30 April 1998
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