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Preliminary
9.3 Status Register (Offset 14h)
The STATUS register can only be read.
Bit
31:22
Name
Name
Bit
Name
C40 INT
OBE IE
IBF IE
TBC IE
C40 IE
OBE INT
IBF INT
TBC INT
C40 INT
INTA
OBF
IBF
MASTER
TBC RDY
CONFIG_L
Document Name:
User Guide
Product Name:
SMT327
Author:
Bill Blyth
Page 16 of 16
21
X
CONFIG_L
Bit
15
14
13
X
X
7
6
5
TBC
IBF
INT
INT
Set if comport output buffer empty interrupts enabled.
Set if comport input buffer full interrupts enabled
Set if JTAG interrupts enabled
Set if interrupt from TIM1 C40 enabled
Set
if
comport
Cleared by writing a 1 to the corresponding bit in the interrupt control
register.
Set
if
comport
Cleared by writing a 1to the corresponding bit in the interrupt control
register
Set
when
Cleared by removing the source of the interrupt in the TBC.
Set
when
the
Cleared by writing a 1 to the corresponding bit in the interrupt control
register.
This is a logical OR of bits 7 to 4 in this register gated with each
ones enable bit.
Set when a word is loaded into the comport output register. Cleared
when the word is transmitted to the C40.
Set when a word is received into the comport input register from the
TIM1 C40.
When set, the comport interface token is owned by the SMT320
bridge.
Reflects the current state of the TBC RDY pin. This bit is active high
and therefore and inversion of the TBC pin.
Reflects the current state of the CONFIG signal from the TIM1 C40.
Active low.
20
19
TBC RDY
0
MASTER
12
11
10
X
X
X
X
4
3
OBE
C40 IE
INT
output
buffer
input
buffer
the
TBC
asserts
TIM1
C40
sets
Issue : 01
Revision Date:
Original Date:
SMT327 User Guide
18
17
16
IBF
OBF
9
8
X
INTA
2
1
0
TBC IE
IBF IE
OBE
IE
becomes
empty.
receives
a
word.
its
interrupt.
its
host
interrupt
8 August, 2000
30 April 1998
bit.
Rev 02
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