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Preliminary
9.2 Control Register (Offset 14h)
The CONTROL register can only be written. It contains flags which control the boot modes of the first TIM
site.
Boot Control
Bit
Name
RESET
IIOF0
IIOF1,
IIOF2
NotNMI
Note. On PCI system reset, RESET is asserted to all TIM sites.
Document Name:
User Guide
Product Name:
SMT327
Author:
Bill Blyth
Page 15 of 15
7-5
4
Not used
notNMI
Write a 1 to this bit to assert the reset signal to all TIM modules on the
SMT320.
These bits connect to the corresponding pins on the first TIM site. These
bits are open-drain and can only pull down. If not required before or after
booting they should be written with 1's.
A 0 written to this bit will assert the active low NMI to the TIM1 C40.
3
2
IIOF2
IIOF1
IIOF0
Issue : 01
Revision Date:
Original Date:
SMT327 User Guide
1
0
RESET
Rev 02
8 August, 2000
30 April 1998
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