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Preliminary
9. Registers
In target mode, the SMT327 is accessed by a host device across the PCI bus. This allows access to the
target mode registers. The operating system or BIOS will normally allocate a base address for the target
mode registers of each SMT327. Access to each register within the SMT327 is then specified by this
base address and the offset shown in the table below.
The I/O address space is decoded as shown in the table below.
Offset
0
+4
+8
+0C
+10
+14
+18
+1C
+20 to +3F
+40 to +7E
+80 to +AF
9.1 Comport Registers (Offset 10h)
The host is connected to the
automatically switch direction to meet a request from either the host or the C40. Both input and output
registers are 32 bits wide. Data can only be written to COMPORT_OUT when STATUS[OBF] is 0. Data
received from the C40 is stored in COMPORT_IN and STATUS[IBF] is set to 1. Reading COMPORT_IN
will clear STATUS[IBF] and allow another word to be received from the C40.
Document Name:
User Guide
Product Name:
SMT327
Author:
Bill Blyth
Page 14 of 14
Register(Write)
-
-
-
-
COMPORT_OUT
CONTROL
INT_CONTROL
-
Not used
Mailbox Write
TBC Write
first TIM site using comport 3. This port is bi-directional and will
Issue : 01
Revision Date:
Original Date:
SMT327 User Guide
Register(Read)
Width
-
-
-
-
COMPORT_IN
STATUS
-
Not used
Mailbox Read
TBC Read
32
32
32
32
16
Rev 02
8 August, 2000
30 April 1998
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