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Preliminary
9.4 Interrupt Control Register (Offset 18h)
This write-only register controls the generation of interrupts on the PCI bus. Each interrupt source has an
associated enable and clear flag. This register can be written with the contents of bits 7:0 of the Status
Register.
Enable Group
Bit
7
Name
CLEAR
C40 INT
IBF IE
OBE IE
TBC IE
C40 IE
CLEAR
OBE INT
CLEAR
IBF INT
CLEAR
C40 INT
The JTAG controller which generates TBC INT must be cleared of all interrupt sources in order to clear the
interrupt.
9.5 Test Bus Controller-TBC (Offsets 80h-AFh)
Refer to the Texas 74ACT8990 data manual for register usage.
The clock for the TBC is ½ the PCI clock rate. So for a standard PCI slot this will therefore clock the
74ATC8990 at 16.67 MHz approximately.
The offsets and write / read capability of all TBC registers is shown below.
Document Name:
User Guide
Product Name:
SMT327
Author:
Bill Blyth
Page 17 of 17
6
5
0
CLEAR
IBF INT
Input Buffer Full Interrupt Enable. Allows an interrupt to be generated
when the host comport input register is loaded with data from the C40.
Output Buffer Empty Interrupt. Allows an interrupt to be generated when
the host comport register has transmitted its contents.
Test Bus Controller Interrupt Enable. Interrupts from the Texas JTAG
controller are enabled when set.
C40 Interrupt Enable. Allows a programmed interrupt to be generated by
the C40 when set.
Write a one to this bit to clear the interrupt resulting from a comport
output event.
Write a one to this bit to clear the interrupt event resulting from comport
input.
Write a one to this bit to clear down the C40 INT event.
4
3
CLEAR
C40 IE
TBC IE
OBE
INT
Issue : 01
Revision Date:
Original Date:
SMT327 User Guide
2
1
0
IBF IE
OBE IE
8 August, 2000
30 April 1998
Rev 02
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