IBM Power 720 Overview page 124

Power capping
Power capping enforces a user-specified limit on power usage. Power capping is not a
power-saving mechanism. It enforces power caps by throttling the processors in the
system, degrading performance significantly. The idea of a power cap is to set a limit that
must never be reached but that frees up extra power, never used in the data center. The
margined
power is this amount of extra power that is allocated to a server during its
installation in a data center. It is based on the server environmental specifications that
usually are never reached because server specifications are always based on maximum
configurations and worst-case scenarios. The user must set and enable an energy cap
from the IBM Director Active Energy Manager user interface.
Soft power capping
There are two power ranges into which the power cap can be set: power capping, as
described previously, and soft power capping. Soft power capping extends the allowed
energy capping range further, beyond a region that can be guaranteed in all configurations
and conditions. If the energy management goal is to meet a particular consumption limit,
then soft power capping is the mechanism to use.
Processor core nap mode
nap,
The IBM POWER7 and POWER7+ processor uses a low-power mode referred to as
which stops processor execution when there is no work to do on that processor core. The
latency of exiting nap mode is small, typically not generating any impact on applications
running. Therefore, the IBM POWER Hypervisor™ can use nap mode as a
general-purpose idle state. When the operating system detects that a processor thread is
idle, it yields control of a hardware thread to the POWER Hypervisor. The POWER
Hypervisor immediately puts the thread into nap mode. Nap mode allows the hardware to
turn the clock off on most of the circuits inside the processor core. Reducing active energy
consumption by turning off the clocks allows the temperature to fall, which further reduces
leakage (static) power of the circuits causing a cumulative effect. Nap mode saves
10 - 15% of power consumption in the processor core.
Processor core sleep mode
To be able to save even more energy, the POWER7+ processor has an even lower power
sleep
mode referred to as . Before a core and its associated private L2 cache enter sleep
mode, the cache is flushed, transition lookaside buffers (TLB) are invalidated, and the
hardware clock is turned off in the core and in the cache. Voltage is reduced to minimize
leakage current. Processor cores inactive in the system (such as CoD processor cores)
are kept in sleep mode. Sleep mode saves about 80% power consumption in the
processor core and its associated private L2 cache.
Processor chip winkle mode
The most amount of energy can be saved when a whole POWER7+ chiplet enters the
winkle
mode, referred to as mode. In this mode the entire chiplet, including the L3 cache is
turned off. This can save more than 95% power consumption.
Fan control and altitude input
System firmware dynamically adjusts fan speed based on energy consumption, altitude,
ambient temperature, and energy savings modes. Power Systems are designed to
operate in worst-case environments, in hot ambient temperatures, at high altitudes, and
with high power components. In a typical case, one or more of these constraints are not
valid. When no power savings setting is enabled, fan speed is based on ambient
temperature and assumes a high-altitude environment. When a power savings setting is
enforced (either Power Energy Saver Mode or Dynamic Power Saver Mode), fan speed
will vary based on power consumption, ambient temperature, and altitude available.
System altitude can be set in IBM Director Active Energy Manager. If no altitude is set, the
system assumes a default value of 350 meters above sea level.
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IBM Power 720 and 740 Technical Overview and Introduction