IBM Power 720 Overview page 198

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RAS feature
Optional ECC I/O hub with freeze behavior
PCI bus extended error detection
PCI bus extended error recovery
PCI-PCI bridge Enhanced Error Handling
Redundant RIO or 12x Channel link
PCI card hot-swap
Dynamic SP failover at run time
Memory sparing with CoD at IPL time
Clock failover run time or IPL
Memory availability
ECC memory, L2, L3 cache
CRC plus retry on memory data bus
Data Bus
Dynamic memory channel repair
Processor memory controller memory scrubbing
Memory page deallocation
Chipkill memory
L1 instruction and data array protection
L2/L3 ECC and cache line delete
Special uncorrectable error handling
Active Memory Mirroring for Hypervisor
Fault detection and isolation
Platform FFDC diagnostics
Run-time diagnostics
Storage Protection Keys
Dynamic Trace
Operating System FFDC
Error log analysis
Freeze mode of I/O Hub
Service processor support for:
Built-in self-tests (BIST) for logic and arrays
Wire tests
Component initialization
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IBM Power 720 and 740 Technical Overview and Introduction
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