Hitachi 42PMA225EZ Service Manual page 34

19 CS#
16, 17, 18 WE#, CAS#,
RAS#
39 x4, x8: DQM
15, 39 x16:
DQMH
20, 21 BA0, BA1
23-26, 29-34, 22, A0-A11
35
2, 4, 5, 7, 8, 10, DQ0-DQ15
11, 13, 42, 44, 45,
47, 48, 50, 51, 53
2, 5, 8, 11, 44, 47, DQ0-DQ7
50, 53
5, 11, 44, 50 DQ0-DQ3
40 NC
36 NC
3, 9, 43, 49 V
DD
6, 12, 46, 52 V
SS
1, 14, 27 V
DD
28, 41, 54 V
SS
Plasma TV Service Manual
Input
Input
Input
DQML,
Input
Input
x16: I/O
x8: I/O
x4: I/O
–
–
Q Supply
Q Supply
Supply
Supply
after exiting the same mode. The input buffers, including CLK,
are disabled during power-down and self refresh modes,
providing low standby power. CKE may be tied HIGH.
Chip Select: CS# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when CS# is registered HIGH. CS# provides for
external bank selection on systems with multiple banks. CS# is
considered part of the command code.
Command Inputs: WE#, CAS#, and RAS# (along with CS#)
define the command being entered.
Input/Output Mask: DQM is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DQM is sampled HIGH during a WRITE
cycle. The output buffers are placed in a High-Z state (two-
clock latency) when DQM is sampled HIGH during a READ
cycle. On the x4 and x8, DQML (Pin 15) is a NC and DQMH is
DQM. On the x16, DQML corresponds to DQ0-DQ7 and
DQMH corresponds to DQ8-DQ15. DQML and DQMH are
considered same state when referenced as DQM.
Bank Address Inputs: BA0 and BA1 define to which bank the
ACTIVE, READ, WRITE or PRECHARGE command is being
applied.
Address Inputs: A0-A11 are sampled during the ACTIVE
command (row-address A0-A11) and READ/WRITE command
(column-address A0-A9 [x4]; A0-A8 [x8]; A0-A7 [x16]; with A10
defining auto precharge) to select one location out of the
memory array in the respective bank. A10 is sampled during a
PRECHARGE command to determine if all banks are to be
precharged (A10[HIGH]) or bank selected by BA0, BA1
(A1[LOW]). The address inputs also provide the op-code
during a LOAD MODE REGISTER command.
Data Input/Output: Data bus for x16 (4, 7, 10, 13, 42, 45, 48,
and 51 are NCs for x8; and 2, 4, 7, 8, 10, 13, 42, 45, 47, 48,
51, and 53 are NCs for x4).
Data Input/Output: Data bus for x8 (2, 8, 47, 53 are NCs for
x4).
Data Input/Output: Data bus for x4.
No Connect: These pins should be left unconnected.
Address input (A12) for the 256Mb and 512Mb devices
DQ Power: Isolated DQ power on the die for improved noise
immunity.
DQ Ground: Isolated DQ ground on the die for improved noise
immunity.
Power Supply: +3.3V ±0.3V.
Ground.
31
11/01/2005