Hitachi 42PMA225EZ Service Manual page 27

IGP0 L14
AOUT M1
V M2
SSA0
V M3
DDA0
V M4
DDD9
V M5
DDD10
ADP7 M6
ADP2 M7
V M8
DDD11
V M9
DDD12
RTS0 M10
V M11
DDD13
AMXCLK M12
FSW M13
ICLK M14
TEST13 N1
TEST14 N2
TEST15 N3
CE N4
LLC2 N5
CLKEXT N6
ADP5 N7
ADP0 N8
SCL N9
RTS1 N10
ASCLK N11
ITRDY N12
TEST16 N13
TEST17 N14
TEST18 P2
EXMCLR P3
LLC P4
RES P5
ADP8 P6
ADP4 P7
ADP1 P8
INT_A P9
SDA P10
AMCLK P11
ALRCLK P12
TEST19 P13
Notes
1. I = input, O = output, P = power, NC = not connected, st = strapping, pu = pull-up, pd = pull-down, od
= open-drain.
Plasma TV Service Manual
O general purpose output signal 0; image port (controlled by
subaddresses 84H and 85H)
O analog test output (do not connect)
P ground for internal Clock Generation Circuit (CGC)
P analog supply voltage (3.3 V) for internal clock generation
circuit
P Digital supply voltage 9 (peripheral cells)
P Digital supply voltage 10 (core)
MSB − 1 of direct analog-to-digital converted output data
O
(VSB)
MSB − 6 of direct analog-to-digital converted output data
O
(VSB)
P Digital supply voltage 11 (peripheral cells)
P Digital supply voltage 12 (core)
O real-time status or sync information, controlled by
subaddresses 11H and 12H
P Digital supply voltage 13 (peripheral cells)
I audio master external clock input
I/pd fast switch (blanking) with internal pull-down inserts
component inputs into CVBS signal
I/O clock
asynchronous back-end clock input
NC do not connect, reserved for future extensions and for testing
I/pu do not connect, reserved for future extensions and for testing
I/pd do not connect, reserved for future extensions and for testing
I/pu chip enable or reset input (with internal pull-up)
O line-locked 1 ¤2 clock output (13.5 MHz nominal)
I external clock input intended for analog-to-digital conversion
of VSB signals (36 MHz)
O MSB - 3 of direct analog-to-digital converted output data
(VSB)
O LSB of direct analog-to-digital converted output data (VSB)
I serial clock input (I 2 C-bus)
O real-time
subaddresses 11H and 12H
O audio serial clock output
I target ready input for image port data
NC do not connect, reserved for future extensions and for testing
NC do not connect, reserved for future extensions and for testing
I/O do not connect, reserved for future extensions and for testing
I/pd external mode clear (with internal pull-down)
O line-locked system clock output (27 MHz nominal)
O reset output (active LOW)
O MSB of direct analog-to-digital converted output data (VSB)
O MSB - 4 of direct analog-to-digital converted output data
(VSB)
O MSB - 7 of direct analog-to-digital converted output data
(VSB)
2
O/od I C-bus interrupt flag (LOW if any enabled status bit has
changed)
I/O/od serial data input/output (I 2 C-bus)
O audio master clock output, up to 50% of crystal clock
O/st/pd audio left/right clock output; can be strapped to supply via a
3.3 kW resistor to indicate
that the default 24.576 MHz crystal (ALRCLK = 0; internal
pull-down) has been replaced
by a 32.110 MHz crystal (ALRCLK = 1); see notes 5 and 7
I/pu do not connect, reserved for future extensions and for testing:
scan input
24
output signal for image
status or sync information,
port, or optional
controlled by
11/01/2005