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SERIAL PORT (2-WIRE)
SDA
SCL
A0
DATA OUTPUTS
RED
GREEN
BLUE
DATA CLOCK OUTPUT
DATACK
INPUTS
RAIN
GAIN
BAIN
HSYNC
VSYNC
SOGIN
CLAMP
Plasma TV Service Manual
AD9883A. Vsync separation is performed via the sync separator.)
Serial Port Data I/O
Serial Port Data Clock
Serial Port Address Input 1
For a full description of the 2-wire serial register and how it works, refer to the 2-
Wire Serial Control Port section.
Data Output, Red Channel
Data Output, Green Channel
Data Output, Blue Channel
The main data outputs. Bit 7 is the MSB. The delay from pixel sampling time to
output is fixed. When the sampling time is changed by adjusting the PHASE
register, the output timing is shifted as well. The DATACK and HSOUT outputs are
also moved, so the timing relationship among the signals is maintained. For exact
timing information, refer to Figures 7, 8, and 9.
Data Output Clock
This is the main clock output signal used to strobe the output data and HSOUT into
external logic. It is produced by the internal clock generator and is synchronous
with the internal pixel sampling clock. When the sampling time is changed by
adjusting the PHASE register, the output timing is shifted as well. The Data,
DATACK, and HSOUT outputs are all moved, so the timing relationship among the
signals is maintained.
Analog Input for Red Channel
Analog Input for Green Channel
Analog Input for Blue Channel
High impedance inputs that accept the Red, Green, and Blue channel graphics
signals, respectively. (The three channels are identical, and can be used for any
colours, but colours are assigned for convenient reference.) They accommodate
input signals ranging from 0.5 V to 1.0 V full scale. Signals should be ac-coupled to
these pins to support clamp operation.
Horizontal Sync Input
This input receives a logic signal that establishes the horizontal timing reference
and provides the frequency reference for pixel clock generation. The logic sense of
this pin is controlled by serial register 0EH Bit 6 (Hsync Polarity). Only the leading
edge of Hsync is active; the trailing edge is ignored. When Hsync Polarity = 0, the
falling edge of Hsync is used. When Hsync Polarity = 1, the rising edge is active.
The input includes a Schmitt trigger for noise immunity, with a nominal input
threshold of 1.5 V.
Vertical Sync Input
This is the input for vertical sync.
Sync-on-Green Input
This input is provided to assist with processing signals with embedded sync,
typically on the Green channel. The pin is connected to a high speed comparator
with an internally generated threshold. The threshold level can be programmed in
10 mV steps to any voltage between 10 mV and 330 mV above the negative peak
of the input signal. The default voltage threshold is 150 mV. When connected to an
ac-coupled graphics signal with embedded sync, it will produce a noninverting
digital output on SOGOUT. (This is usually a composite sync signal, containing
both vertical and horizontal sync information that must be separated before
passing the horizontal sync signal to Hsync.) When not used, this input should be
left unconnected. For more details on this function and how it should be
configured, refer to the Sync-on-Green section.
External Clamp Input
This logic input may be used to define the time during which the input signal is
clamped to ground. It should be exercised when the reference dc level is known to
be present on the analog input channels, typically during the back porch of the
graphics signal. The CLAMP pin is enabled by setting control bit Clamp Function to
1, (register 0FH, Bit 7, default is 0). When disabled, this pin is ignored and the
clamp timing is determined internally by counting a delay and duration from the
18
11/01/2005
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