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V
F11
SSD6
V
F12
DDD6
HPD5
F13
HPD6
F14
AI34
G1
V
G2
DDA3A
AI22
G3
AI21
G4
V
G11
SSD7
IPD1
G12
HPD7
G13
IPD0
G14
AI2D
H1
AI23
H2
V
H3
SSA2
V
H4
DDA2
IPD2
H11
V
H12
DDD7
IPD4
H13
IPD3
H14
V
J1
DDA2A
AI11
J2
AI24
J3
V
J4
SSA1
V
J11
SSD8
V
J12
DDD8
IPD6
J13
IPD5
J14
AI12
K1
AI13
K2
AI1D
K3
V
K4
DDA1
IPD7
K11
IGPH
K12
IGP1
K13
IGPV
K14
V
L1
DDA1A
AGNDA
L2
AI14
L3
V
L4
SSD9
V
L5
SSD10
ADP6
L6
ADP3
L7
V
L8
SSD11
V
L9
SSD12
RTCO
L10
V
L11
SSD13
ITRI
L12
IDQ
L13
Plasma TV Service Manual
P
Digital ground 6 (core)
P
Digital supply voltage 6 (core)
I/O
MSB - 2 of host port data I/O, extended C
expansion port, extended C
I/O
MSB - 1 of host port data I/O, extended C
expansion port, extended C
I
analog input 34
P
analog supply voltage for analog inputs AI3x (3.3 V)
I
analog input 22
I
analog input 21
P
Digital ground 7 (peripheral cells)
O
MSB - 6 of image port data output
I/O
MSB of host port data I/O, extended C
expansion port, extended C
O
LSB of image port data output
I
differential input for ADC channel 2 (pins AI24 to AI21)
I
analog input 23
P
ground for analog inputs AI2x
P
analog supply voltage for analog inputs AI2x
O
MSB - 5 of image port data output
P
Digital supply voltage 7 (peripheral cells)
O
MSB - 3 of image port data output
O
MSB - 4 of image port data output
P
analog supply voltage for analog inputs AI2x
I
analog input 11
I
analog input 24
P
ground for analog inputs AI1x
P
Digital ground 8 (core)
P
Digital supply voltage 8 (core)
MSB − 1 of image port data output
O
O
MSB − 2 of image port data output
I
analog input 12
I
analog input 13
I
differential input for ADC channel 1 (pins AI14 to AI11)
P
analog supply voltage for analog inputs AI1x (3.3 V)
O
MSB of image port data output
O
multi purpose horizontal reference output signal; image port
(controlled by subaddresses 84H and 85H)
O
general purpose output signal 1; image port (controlled by
subaddresses 84H and 85H)
O
multi purpose vertical reference output signal; image port
(controlled by subaddresses 84H and 85H)
P
analog supply voltage for analog inputs AI1x (3.3 V)
P
analog signal ground
I
analog input 14
P
Digital ground 9 (peripheral cells)
P
Digital ground 10 (core)
O
MSB - 2 of direct analog-to-digital converted output data
(VSB)
O
MSB - 5 of direct analog-to-digital converted output data
(VSB)
P
Digital ground 11 (peripheral cells)
P
Digital ground 12 (core)
O/st/pd
real-time control output; contains information about actual
system clock frequency, field rate, odd/even sequence,
decoder status, subcarrier frequency and phase and PAL
sequence; the RTCO pin is enabled via I
see notes 5, 6
P
Digital ground 13 (peripheral cells)
I/(O)
image port output control signal, affects all input port pins
inclusive ICLK, enable and active polarity is under software
control (bits IPE in subaddress 87H); output path used for
testing: scan output
O
output data qualifier for image port (optional: gated clock
output)
23
-C
B
R
-C
output for image port
B
R
-C
B
R
-C
output for image port
B
R
-C
R input for
B
R
-C
output for image port
B
R
2
C-bus bit RTCE;
11/01/2005
input for
input for
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