Memory Mirroring - IBM System x3550 M3 Type 4254 Installation And User Manual

Memory mirroring

Memory-mirroring mode replicates and stores data on two pairs of DIMMs within
two channels simultaneously. If a failure occurs, the memory controller switches
from the primary pair of memory DIMMs to the backup pair of DIMMs.
To enable memory mirroring through the Setup utility, select System Settings >
Memory. For more information, see "Using the Setup utility" on page 112. When
you use the memory mirroring feature, consider the following information:
v When you use memory mirroring, you must install a pair of DIMMs at a time.
v Channel 2, DIMM connectors 7, 8, 9, 16, 17, and 18 are not used in
v The maximum available memory is reduced to half of the installed memory
The following diagram shows the memory channel interface layout with the
DIMM installation sequence for mirroring mode. The numbers within the boxes
indicate the DIMM population sequence in pairs within the channels, and the
numbers next to the boxes indicate the DIMM connectors within the channels. For
example, the following illustration shows the first pair of DIMMs (indicated by
ones (1) inside the boxes) should be installed in DIMM connectors 1 on channel 0
and DIMM connector 2 on channel 1. DIMM connectors 3, 6, 9, 12, 15, and 18 on
channel 2 are not used in memory-mirroring mode.
Figure 30. Memory channel interface layout
The following table lists the DIMM connectors on each memory channel.
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IBM System x3550 M3 Type 4254 and 7944: Installation and User's Guide
One DIMM must be in channel 0, and the mirroring DIMM must be in the same
slot in channel 1. The two DIMMs in each pair must be identical in size, type,
and rank (single or dual), and organization, but not in speed. The channels run
at the speed of the slowest DIMM in any of the channels.
memory-mirroring mode.
when memory mirroring is enabled. For example, if you install 64 GB of
memory using RDIMMs, only 32 GB of addressable memory is available when
you use memory mirroring.
1 2 3
CH0
3 2 1
CPU1
CH1
1 2 3
6 5 4
CH2
9 8 7
Table 11. Connectors on each memory channel
Memory channel
Channel 0
Channel 1
Channel 2
6 5
CH0
10
CPU2
QPI
6 5
CH1
13
CH2
16
DIMM connector
1, 2, 3, 10, 11, 12
4, 5, 6, 13, 14, 15
7, 8, 9, 16, 17, 18
4
11 12
4
14 15
17 18