Pll Circuits - Icom IC-756PRO Service Manual

The ALC bias voltage is also applied to the ALC meter ampli-
fier (IC551a, pin 2) to obtain an ALC meter signal (ALCL).
The amplified signal is passed through the analog switch (IC
3631, pins 13, 14) and applied to the main CPU (IC3501, pin
108) to drive the S/RF meter via the sub CPU (IC401) on the
DISPLAY board.
An external ALC input from the [ALC] jack or [ACC] sockets
is applied to the buffer amplifier (Q521). External ALC oper-
ation is identical to that of the internal ALC.
The FORV signal is also applied to the power meter amplifi-
er (IC571a, pin 3). The amplified signal is passed through
the analog switch (IC3631, pins 1, 15) as an FORL signal
and applied to the main CPU (IC3501, pin 109) to drive the
S/RF meter when the power meter is selected.
3-2-9 APC CIRCUIT (MAIN UNIT)
The APC (Automatic Power Control) circuit protects the
power amplifiers on the PA unit from high SWR and exces-
sive current.
The reflected wave signal appears and increases when the
connected antenna is mismatched to 50 Ω. The APC detec-
tor circuit (CTRL unit; D1 and L1) detects the reflected sig-
nal, and applies it to the APC circuit (IC551c, pin 9) as a
REFV signal.
When the REFV signal level increases, the APC circuit
decreases the ALC voltage to activate the APC.
For the current APC, the power transistor current is obtained
by detecting the voltages (ICH and ICL) which appear at
both terminals of the current detector (PA unit, R28). The
detected voltages are applied to the differential amplifier
(IC551d, pins 12, 13). When the current of transistors is
increased, the amplifier controls the ALC line to prevent
excessive current flow.
A portion of the REFV signal is applied to the SWR meter
amplifier (IC571b, pin 5). The amplified signal is passed
through the analog switch (IC3631, pins 3, 4) as an REFL
signal and applied to the main CPU (IC3501, pin 110) to
drive the S/RF meter when the SWR meter is selected.
3-2-10 TEMPERATURE PROTECTION CIRCUIT
(PA UNIT)
The cooling fan (MF1) is activated while transmitting or
when the temperature of the power amplifier exceeds the
preset value. The temperature protection circuit consists of
Q10–Q13 and R50.
While transmitting, Q10 and Q12 are turned ON, and pro-
vide a voltage to the cooling fan to rotate at medium speed.
The thermistor detects the temperature of Q5, and activates
Q11 and Q13 to accelerate the cooling fan when the detect-
ed temperature exceeds 70˚C (158˚F). The cooling fan
rotates at high speed at 80˚C (176˚F) or more.
The thermistor keeps the cooling fan rotating even while
receiving until the Q5 temperature drops to 60˚C (140˚F) or
below.
3-2-11 MONITOR CIRCUIT
(DSP BOARD AND MAIN UNIT)
The microphone audio signals can be monitored to check
voice characteristics.
(1) When FM/AM modes (MAIN UNIT)
A portion of the microphone audio signals from the VCA sec-
tion in IC451 are applied to the analog switch (IC361). The
selected audio signals are applied to IC371 (pin 2), and the
output signals from pin 9 are applied to the AF amplifier cir-
cuit (IC311, pin 7).
(2) When SSB/RTTY modes (DSP BOARD)
A portion of the transmit IF signal from the low-pass filter
(IC2381c/d) is amplified at the IF (IC2381b) and buffer
(IC2381a) amplifiers and applied to the digital mixer circuit
(IC2302). The applied signal is mixed with a 36 kHz LO sig-
nal from IC2347 to demodulate into the AF signals. The
demodulated signals are passed through the buffer amplifi-
er (IC2381a), low-pass filter (IC2441b/c) and AF amplifier
(IC2441d), and then applied to the MAIN unit as the DMAF
signal.
The DMAF signal from the DSP board is amplified at ALC
amplifier (MAIN unit; IC372) and applied to the VCA section
of IC371 (MAIN unit). The volume controlled AF signals is
applied to the AF amplifier circuit (MAIN unit; IC311, pin 7).

3-3 PLL CIRCUITS

3-3-1 GENERAL
The PLL unit generates a pair of 1st LO frequencies
(64.485–124.455 MHz) for dualwatch and spectrum scope
functions; a 2nd LO frequency (64 MHz), 3rd LO frequency
(491 kHz) and sweep LO frequency for the spectrum scope
function.
The 1st LO PLLs adopt a mixer-less dual loop PLL system
and has 4 VCO circuits. The LOs, except the 2nd, use DDSs
while the 2nd LO uses the fixed frequency of the crystal
oscillator.
3-3-2 1ST LO PLL CIRCUIT
The 1st LO PLLs contain a main and reference loop as a
dual loop system. Both PLLs have equivalent circuits— this
manual describes only the 1st LO PLL A circuit.
The reference loop generates a 10.747 to 10.865 MHz fre-
quency using a DDS circuit, and the main loop generates a
64.485 to 124.455 MHz frequency using the reference loop
frequency.
(1) REFERENCE LOOP PLL
The oscillated signal at the reference VCO (Q151, D151) is
amplified at the amplifiers (Q152, Q102) and is then applied
to the DDS IC (IC101, pin 46). The signal is then divided and
detected on phase with the DDS generated frequency.
The detected signal output from the DDS IC (pin 56) is con-
verted into DC voltage (lock voltage) at the loop filter
(R135–R137, C121, C151) and then fed back to the refer-
ence VCO circuit (Q151, D151).
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