Sony DIGITAL BETACAM DVW-707 Maintenance Manual page 110

Average value and peak value of the video signal that are
detected by the process IC, are sent to the camera CPU
through data bus.
The detected data is processed by the camera CPU and sent
to the process IC and to the VA-191 board together with
the SDA (CCD signal) or through data bus.
The control CPU implements various controls over the
camera block in accordance with the instructions that are
memorized in ROM. The control CPU interprets the
function switch instructions, analog data etc., and outputs
the various control signals. It also writes the status
information and self-diagnostics information into the
character generator, and outputs them as the character data.
The control CPU allows the RM-P9 (optional) and the VA-
DN1 (optional) to be connected through external equip-
ment RM-B150 (optional) or the conversion cable (option-
al).
ES-23 board
The ES-23 board consists of the following circuits.
. The circuit that encodes that composite signal from the
analog component signals which are supplied by the D/A
converter in the DCP-17 board.
. PLL circuit for subcarrier clock signal
Most adjustment controls are replaced by electronic
controls that allow most of adjustments to be executed
using the setup menu.
The ES-23 board contains the sync separator IC and others
that synchronizes the entire system with the external input
video signal which is input at the GENLOCK IN connec-
tor.
RC-69 board, RC-75 board
(For DVW-790WS/790WSP/709WS/709WSP only)
The RC-69 board and RC-75 board consist of the circuit
that converts signal rate of the digital component signals
from the DCP-17 board, that of the VF video signal and
that of the detail signal for VF video from the 18 MHz to
the 13.5 MHz. The RC-69 board and RC-75 board has the
built-in FIFO IC.
6-2
(2) RF Processing Block
(DVP-17 board (1/3) and Drum assembly)
The Digital Betacam Camcorder records video and audio
signals on the tape using the Digital Betacam format.
In a Digital Betacam studio VTR, one pair of heads with
an azimuth angle in the opposite direction to each other
record two tracks at a time by turns with another one pair
of heads on the opposite side of the rotary drum every time
the drum rotates by a half turn, and record one-field data
every time the drum rotates by 1.5 turns (i.e., on six helical
tracks).
As compared with that, to reduce an acoustic noise, the
Digital Betacam Camcorder makes the drum rotation 1/2
time as small as the studio VTR and makes the number of
heads two times (eight heads) as large. In other words,
four-in-a-pair heads record data simultaneously on four
tracks by the hour two times as long as usually.
The tape recorded in such a way can be directly played
back by the studio VTR. To play back the tape by this
VTR, however, eight PB heads are required. This system
requires the time-base conversion (rate conversion) for
REC/PB data. The RF Processing Block executes the time-
base conversion.
In the REC mode, this block converts the two-channel
parallel REC data sent from the Digital Processing Block
(DVP-14 board) in rate into 1/2 and distributes it to four-
channel serial REC data. In the PB mode, this block
multiplexes four-channel serial PB data and converts it into
the two-channel parallel PB data (CONF DATA) of the
normal rate.
The RF processing block also encodes the control data sent
from Control Blocks to an MPX signal, sends it to the
Drum assembly to control REC/PB amplifiers.
DVW-790WS/709WS/707
DVW-790WSP/709WSP/707P P1