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Problem:
Bits SWDPIO_EXT[7:4] of Initialization Control Word 2 in the EEPROM are supposed to map to bits
SWDPIOHI[11:8] in the Extended Device Control Register at offset 0x00018. Instead, the bits map to
SWDPINSHI[7:4] of that register.
Implication:
The input/output characteristic of some of the software-defined pins could be assigned incorrectly.
Workaround:
Program these bits in the Extended Device Control Register correctly in software.
Status:
Intel does not plan to resolve this erratum in a future stepping of the 82543GC Gigabit Ethernet Controller.
25. Continuous XOFFs Transmitted When Receive Buffer Is Full
Problem:
When the receive FIFO is full (or within a quad word of full), the 82543GC controller will send XOFFs
continuously. The receive buffer will fill up if there are insufficient receive descriptors or insufficient memory
buffers. This condition can occur under heavy network traffic loads.
Implication:
When the controller is sending continuous XOFFs, it cannot transmit any data packets in the transmit FIFO.
Workaround:
Set up a watchdog timer in the software driver to monitor that packets given to the 82543GC device are actually
transmitted. If packet transmission is not acknowledged after 2-3 seconds, the host system should be notified to
reset the Ethernet controller. At this time, the driver should return memory resources to the operating system for
reallocation.
Status:
Intel does not plan to resolve this erratum in a future stepping of the 82543GC Gigabit Ethernet Controller.
26. Default Speed Selection May Depend on EEPROM Presence
Problem:
When the controller is configured for GMII operation and auto-speed detection is disabled, the default speed
setting (CTRL.SPEED) will depend on whether a valid EEPROM is present, as determined by the signature bits.
If a legitimate EEPROM is determined not to be present, the controller will use 10b as the speed selection bits
in the Device Control Register, resulting in a speed of 1000 Mb/s. If an EEPROM is determined to be present,
the controller will use 00b as the speed selection bits, resulting in a speed of 10 Mb/s.
Implication:
This erratum could cause the 82543GC controller to initially be configured at the wrong speed if it is being used
in an application for twisted pair copper wiring. Note that the 82543GC device has another erratum related to
EEPROM detection (Erratum #29, "Initialization Ignores Wrong EEPROM Signature"). Employing the
workaround to Erratum #29 requires an EEPROM to be present in all 82543GC designs. Thus, the default
speed setting is most likely to be seen as 10 Mb/s.
Workaround:
Software should program the CTRL.SPEED bits to the desired speed and not expect the controller to default to
gigabit.
Status:
Intel does not plan to resolve this erratum in a future stepping of the 82543GC Gigabit Ethernet Controller.
27. Link Status Change Interrupt Only Occurs If Link is Up
Problem:
If link is lost, the controller may not always generate a link status change interrupt. This erratum only applies to
the TBI (fiber) mode of operation.
Implication:
The system may fail to notice loss of link if it relies solely on receiving an interrupt as notification.
Workaround:
The Interrupt Cause Status Register will correctly indicate a link status change event even if the interrupt does
not occur. The software driver can query this register. The software driver can also look for sequence errors as
an indication that link has been lost.
Status:
Intel does not plan to resolve this erratum in a future stepping of the 82543GC Gigabit Ethernet Controller.
28. Early Transmit Feature Does Not Operate Correctly
82543GC Gigabit Ethernet Controller Specification Update
17
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