Dma Channels; Fixed I/O Map; I/O Map - Intel D865PCD Technical Product Specification

Intel Desktop Board D865PCD Technical Product Specification

2.3 DMA Channels

Table 11.

DMA Channels

DMA Channel Number
0
1
2
3
4
5
6
7

2.4 Fixed I/O Map

Table 12.

I/O Map

Address (hex)
0000 - 00FF
0170 - 0177
01F0 - 01F7
0228 - 022F (Note 1)
(Note 1)
0278 - 027F
(Note 1)
02E8 - 02EF
(Note 1)
02F8 - 02FF
0374 - 0377
0377, bits 6:0
0378 - 037F
03B0 - 03BB
03C0 - 03DF
03E8 - 03EF
03F0 - 03F5
03F4 – 03F7
03F8 - 03FF
04D0 - 04D1
LPTn + 400
(Note 2)
0CF8 - 0CFB
(Note 3)
0CF9
0CFC - 0CFF
FFA0 - FFA7
FFA8 - FFAF
Notes:
1. Default, but can be changed to another address range
2. Dword access only
3. Byte access only
38
Data Width
8 or 16 bits
8 or 16 bits
8 or 16 bits
8 or 16 bits
8 or 16 bits
16 bits
16 bits
16 bits
Size Description
256 bytes Used by the Desktop Board D865PCD. Refer to the ICH5
data sheet for dynamic addressing information.
8 bytes Secondary Parallel ATA IDE channel command block
8 bytes Primary Parallel ATA IDE channel command block
8 bytes LPT3
8 bytes LPT2
8 bytes COM4
8 bytes COM2
4 bytes Secondary Parallel ATA IDE channel control block
7 bits Secondary IDE channel status port
8 bytes LPT1
12 bytes Intel 82865P MCH
32 bytes Intel 82865P MCH
8 bytes COM3
6 bytes Diskette channel
1 byte Primary Parallel ATA IDE channel control block
8 bytes COM1
2 bytes Edge/level triggered PIC
8 bytes ECP port, LPTn base address + 400h
4 bytes PCI configuration address register
1 byte Reset control register
4 bytes PCI configuration data register
8 bytes Primary Parallel ATA IDE bus master registers
8 bytes Secondary Parallel ATA IDE bus master registers
System Resource
Open
Parallel port
Diskette drive
Parallel port (for ECP or EPP)
DMA controller
Open
Open
Open