Intel 8086 Specification Sheet page 15

A C CHARACTERISTICS
MINIMUM COMPLEXITY SYSTEM TIMING REQUIREMENTS
Symbol Parameter
TCLCL CLK Cycle Period
TCLCH CLK Low Time
TCHCL CLK High Time
TCH1CH2 CLK Rise Time
TCL2CL1 CLK Fall Time
TDVCL Data in Setup Time
TCLDX Data in Hold Time
TR1VCL RDY Setup Time
into 8284A (See
Notes 1 2)
TCLR1X RDY Hold Time
into 8284A (See
Notes 1 2)
TRYHCH READY Setup
Time into 8086
TCHRYX READY Hold Time
into 8086
TRYLCL READY Inactive to
CLK (See Note 3)
THVCH HOLD Setup Time
TINVCH INTR NMI TEST
Setup Time (See
Note 2)
TILIH Input Rise Time
(Except CLK)
TIHIL Input Fall Time
(Except CLK)
(8086 T 0 C to 70 C V
e
A
(8086-1 T 0 C to 70 C V
e
A
(8086-2 T 0 C to 70 C V
e
A
8086 8086-1
Min Max Min Max
200 500 100 500
118 53
69 39
10 10
10 10
30 5
10 10
35 35
0 0
118 53
30 20
8 10
b b
35 20
30 15
20 20
12 12
5V 10%)
e
g
CC
5V 5%)
e
g
CC
5V 5%)
e
g
CC
8086-2
Units Test Conditions
Min Max
125 500 ns
68 ns
44 ns
10 ns From 1 0V to 3 5V
10 ns From 3 5V to 1 0V
20 ns
10 ns
35 ns
0 ns
68 ns
20 ns
8 ns
b
20 ns
15 ns
20 ns From 0 8V to 2 0V
12 ns From 2 0V to 0 8V
8086
15