Reset Timing - Intel 8086 Specification Sheet

8086
WAVEFORMS
(Continued)
ASYNCHRONOUS SIGNAL RECOGNITION
NOTE
1 Setup requirements for asynchronous signals only to guarantee recognition at next CLK
BUS LOCK SIGNAL TIMING (MAXIMUM MODE
ONLY)
REQUEST GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)
NOTE
The coprocessor may not drive the buses outside the region shown without risking contention
24

RESET TIMING

231455– 18
231455 –17
231455 –19
231455 –20