Intel 8086 Specification Sheet page 23

WAVEFORMS
(Continued)
MAXIMUM MODE (Continued)
NOTES
1 All signals switch between V
2 RDY is sampled near the end of T
3 Cascade address is valid between first and second INTA cycle
4 Two INTA cycles run back-to-back The 8086 LOCAL ADDR DATA BUS is floating during both INTA cycles Control for
pointer address is shown for second INTA cycle
5 Signals at 8284A or 8288 are shown for reference only
6 The issuance of the 8288 command and control signals (MRDC MWTC AMWC IORC IOWC AIOWC INTA and DEN)
lags the active high 8288 CEN
7 All timing measurements are made at 1 5V unless otherwise noted
8 Status inactive in state just prior to T
and V unless otherwise specified
OH OL
T T to determine if T
2 3 W
4
machines states are to be inserted
W
8086
231455 –16
23