Cache Control Page (38 H ) - Seagate MEDALIST 1080SL Product Manual

Medalist 1080sl SCSI Product Manual, August 1995
C.9 Cache Control page (38
The Cache Control page is shown below. This table summarizes the
function, the default value and the changeability of each bit.
Bytes
7
0 PS (1)
1
2 Rsrvd WIE Rsrvd
default 0
changeable
3 (default)
changeable
4 (default)
changeable
5 (default)
changeable
6 (default)
changeable
7 (default)
changeable
8–15 (default)
changeable
Byte 2 The cache enable (CE) bit is always the inverse of the RCD bit
in Mode page 08
H
The write index enable (WIE) bit controls the creation of cache
data on Write commands. If bit 6 is 0, the next command treats
the cache area as empty.
The cache table size field contains the same values as Mode
page 08 , byte 13, bits 3 through 0.
H
Byte 3 The prefetch threshold is not implemented. The drive reads until
the buffer is full upon receipt of a Read command.
Byte 4 The maximum prefetch field always contains the same value as
byte 9 of the Caching page. The initiator cannot change this byte
directly.
)
H
Bits
6 5 4 3
Page code (38
Page length (0E
H
CE Cache table size
0 0 1 0
(00 )
H
Prefetch threshold (00
00
H
Maximum prefetch (FF
00
H
Maximum prefetch multiplier (00
00
H
Minimum prefetch (00
00
H
Minimum prefetch multiplier (00
00
H
Reserved (0000000000000000
0000000000000000
.
97
2 1 0
)
H
)
0 0 1
)
H
)
H
)
H
)
H
)
H
)
H
H