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1.3 Programmable Gain Amplifier Gain Control
Each channel of the THS7002 IC is provided with three digital control inputs
for setting the gain of the PGA stage (AG0 – AG2 and BG0 – BG2). Standard
TTL or CMOS Logic signals operate these control inputs. The gain control
inputs are not latched and respond to the control signals in real time.
Therefore, the control signals on these inputs must remain constant if the PGA
gain is to remain constant. For stand-alone evaluation of this function, onboard
DIP switches (S1:A to S1:C and S2:A to S2:C) are used to control the gain for
each PGA. Note that all DIP switch gain control elements must be set to OFF
if gain is to be set by digital control signals. For convenience, test points (TP2
– TP4 and TP9 – TP11) are placed on each of these lines to allow easy external
connections. There are 330-
control input pins. These were added only for surge suppression and are not
required for actual system design. Nominal gain/attenuation is shown in
Table 1–1.
Table 1–1. THS7002 EVM PGA Nominal Gain/Attenuation
G2
G1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
One aspect of the THS7002 PGA signal inputs that must be considered is that
there are internal variable resistors (RF and RG) that set the gain. The
resistance of RG changes from about 270
(gain = –22 dB). Therefore, any source impedance at the input to the PGA
amplifiers will cause a gain error to be seen at the output. A buffer/amplifier is
highly recommended to directly drive the input of the PGA section to help
minimize this effect.
Another consideration is that when each amplifier VREF is connected to
ground, the internal RG resistor is connected to a virtual ground. Therefore,
if a termination resistor is used on the source side, the total terminating
resistance is the parallel combination of the terminating resistance and the
internal RG resistor. This, in conjunction with the series impedance problem
mentioned previously, can potentially cause a voltage mismatch between the
output of a 50- source and the expected PGA output voltage.
These points are illustrated by the following formula and in the simplified
diagram of the THS7002 PGA section shown in Figure 1–4.
R
G0
PGA Gain (dB)
0
1
0
1
0
1
0
1
+
R
TERMINATION
TOTALTERMINATION
R
TERMINATION
Programmable Gain Amplifier Gain Control
isolation resistors in series with each IC gain
PGA Gain (V/V)
–22
–16
–10
–4
2
8
14
20
(gain = +20 dB) to about 3 k
)
(R
R
)
)
)
SOURCE
G
(R
R
)
SOURCE
G
General Information
0.08
0.16
0.32
0.63
1.26
2.52
5.01
10
(3)
1-7
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