Texas Instruments Boomer LM49360 Manuals

Manuals and User Guides for Texas Instruments Boomer LM49360. We have 1 Texas Instruments Boomer LM49360 manual available for free PDF download: User Manual

Texas Instruments Boomer LM49360 User Manual (137 pages)

Mono Class D Audio Codec PMU with Ground Referenced Headphone Amplifiers, Earpiece Driver, Audio DSP, 2 Step-Down DC-DC Converters, and 7 LDO Regulators

Brand: Texas Instruments | Category: Amplifier | Size: 2.46 MB

General Description
2
Applications
2
Key Specifications
2
Features
2
LM49360 Overview
3
FIGURE 1. LM49360 Block Diagram
3
Typical Application
4
FIGURE 2. Sub PMU System Diagram
4
FIGURE 3. AP PMU System Diagram
5
Table of Contents
7
Connection Diagrams
11
Pin Type Definitions
14
State Machine Description
15
Pmu State Machine Description
15
FIGURE 4. PMU State Machine
16
Audio Pmc State Machine Description
17
State_0 (OFF)
17
State_1 (BIAS)
17
FIGURE 5. LM49360 Audio PMC Sequencer Overview with Typical Timing
17
State_2 (AMPS ON)
18
Amplifier Control Fsm
18
State_3 (UNMUTE)
18
State_4 (ON)
18
State_5 (MUTE)
18
State_6 (AMPS_OFF)
18
State_7 (OFF)
18
FIGURE 6. Zero Cross Detect Comparator (ZXD)
18
Absolute Maximum Ratings
19
Operating Ratings
19
Total Shutdown Current Consumption
19
PMU Current Consumption
19
Thermal Shutdown
20
Under Voltage Lock out
20
Logic and Control
20
Electrical Characteristics / Buck Converters
21
Electrical Characteristics / General Ldos 1 to 6
21
Electrical Characteristics / High Input Low Output LDO 7
22
Electrical Characteristics / Audio CODEC: A_V
23
DD = Ls_V
23
DD = D_V
23
Timing Characteristics: DV DD = I/OV DD
28
Typical Performance Characteristics
30
System Control
39
Input Power Sequencing
39
I 2 C Signals
39
I 2 C Data Validity
39
C Start and Stop Conditions
39
Transferring Data
39
FIGURE 7. I 2 C Signals: Data Validity
39
FIGURE 8. I 2 C Start and Stop Conditions
39
FIGURE 9. I2C Chip Address
39
FIGURE 10. Example I C Write Cycle
40
FIGURE 11. Example I C Read Cycle
40
FIGURE 12. I 2 C Timing Diagram
40
I 2 C Timing Parameters
41
Power on Sequence
41
FIGURE 13. Simplified Startup Sequence if CONFIG = H or Z (SUB_PMU)
41
FIGURE 14. Simplified Startup Sequence if CONFIG = L (PMU)
42
FIGURE 15. LM493060A CONFIG = H Start-Up Sequence
43
FIGURE 16. LM49360A CONFIG = L Start-Up Sequence
44
FIGURE 17. LM49360A CONFIG = Z Start-Up Sequence
45
Device Register Map
47
TABLE 1. PMU Register Map
47
TABLE 2. Audio Register Map
48
TABLE 3. Nonzero I 2 C Default Registers
51
Sleep Enables
52
TABLE 4. 0X00H PMU Setup
52
TABLE 5. NV BANK (0X01H)
52
TABLE 6. SLEEP 1 (0X02H)
52
LDO Flags and Bypass Pulse Control
53
TABLE 7. FLAGS 1 (0X03H)
53
TABLE 8. FLAGS 2 (0X04H)
53
TABLE 9. BYPASS (0X05H)
53
TABLE 10. SWOVR 1 (0X06H)
53
Sequence and Voltage Programming (Banks 0 to 2)
54
TABLE 11. SWOVR 2 (0X07H)
54
TABLE 12. Enb1Bank 0: CONFIG = Z (0X10H) Bank 1: CONFIG = H (0X20H)Bank 2: CONFIG = L (0X30H)
54
FIGURE 18. Typical PWM Operation
55
FIGURE 19. Typical ECO Operation
56
TABLE 13. Buck 1 and Buck 2 Operation
56
TABLE 14. ENB2 Bank 0: CONFIG = Z (0X11H) Bank 1: CONFIG = H (0X21H)Bank 2: CONFIG = L (0X31H)
56
TABLE 15. Bk1Vbank 0: CONFIG = Z (0X12H)Bank 1: CONFIG = H (0X22H)Bank 2: CONFIG = L (0X32H)
57
TABLE 16. BK2V Bank 0: CONFIG = Z (0X13H)Bank 1: CONFIG = H (0X23H)Bank 2: CONFIG = L (0X33H)
57
TABLE 17. LDO1 - 6 Bank 0: CONFIG = Z (0X14H:ldo1) (0X19H:ldo6)Bank 1: CONFIG = H (0X24H:ldo1) (0X29H:ldo6)Bank 2: CONFIG = L (0X34H:ldo1) (0X39H:ldo6)
60
TABLE 18. LDO7 Bank 0: CONFIG = Z (0X1Ah) Bank 1: CONFIG = H (0X2Ah)Bank 2: CONFIG = L (0X3Ah)
61
TABLE 19. Thresbank 0: CONFIG = Z (0X1Bh)Bank 1: CONFIG = H (0X2Bh)Bank 2: CONFIG = L (0X3Bh)
62
TABLE 20. Pldwnbank 0: CONFIG = Z (0X1Ch)Bank 1: CONFIG = H (0X2Ch)Bank 2: CONFIG = L (0X3Ch)
62
TABLE 21. Ovrbank 0: CONFIG = Z (0X1Dh)Bank 1: CONFIG = H (0X2Dh)Bank 2: CONFIG = L (0X3Dh)
62
TABLE 22. Subovrbank 0: CONFIG = Z (0X1Eh)Bank 1: CONFIG = H (0X2Eh)
63
TABLE 23. I 2 C1 (0X40H)
63
TABLE 24. I 2 C2 (0X41H)
64
TABLE 25. BK1_FPWM (0X5Ah)
64
Basic PMC Setup Register
65
TABLE 26. BK2_FPWM (0X5Eh)
65
TABLE 27. PMC_SETUP (0X00H)
65
PMC Clocks Register
66
PMC Clock Divide Register
66
TABLE 28. PMC_SETUP (0X01H)
66
TABLE 29. PMC_SETUP (0X02H)
66
LM49360 Clock Network
67
TABLE 30. DAC Clock Requirements
67
TABLE 31. ADC Clock Requirements
67
FIGURE 20. Internal Clock Network
68
PLL Setup Registers
69
FIGURE 21. PLL Loop
69
TABLE 32. PLL Settings for Common System Clock Frequencies
70
TABLE 33. PLL_CLOCK_SOURCE (0X03H)
71
TABLE 34. PLL_M (0X04H)
71
TABLE 35. PLL_N (0X05H)
71
TABLE 36. PLL_N_MOD (0X06H)
72
TABLE 37. PLL_P1 (0X07H)
72
TABLE 38. PLL_P2 (0X08H)
72
Analog Mixer Control Registers
73
TABLE 39. CLASS_D_OUTPUT (0X10H)
73
TABLE 40. LEFT HEADPHONE_OUTPUT (0X11H)
73
TABLE 41. RIGHT HEADPHONE_OUTPUT (0X12H)
74
TABLE 42. AUX_OUTPUT (0X13H)
74
TABLE 43. OUTPUT_OPTIONS (0X14H)
75
TABLE 44. ADC_INPUT (0X15H)
75
TABLE 45. MIC_INPUT (0X16H)
76
TABLE 46. AUX_LEVEL (0X18H)
77
TABLE 47. MONO_LEVEL (0X19H)
78
FIGURE 22. Application Circuit for Headphone Detection
79
TABLE 48. HP_SENSE (0X1Bh)
80
ADC Control Registers
81
TABLE 49. ADC Basic (0X20H)
81
TABLE 50. ADC_CLK_DIV (0X21H)
81
TABLE 51. ADC_MIXER (0X23H)
82
DAC Control Registers
83
TABLE 52. DAC Basic (0X30H)
83
TABLE 53. DAC_CLK_DIV (0X31H)
83
Digital Mixer Control Registers
84
FIGURE 23. Digital Mixer
84
TABLE 54. Input Levels 1 (0X40H)
85
TABLE 55. Input Levels 2 (0X41H)
85
TABLE 56. Audio Port 1 Input (0X42H)
86
TABLE 57. Audio Port 2 Input (0X43H)
86
TABLE 58. DAC Input Select (0X44H)
87
TABLE 59. Decimator Input Select (0X45H)
87
Audio Port Control Registers
88
FIGURE 24. I 2 S Serial Data Format (24 Bit Example)
88
FIGURE 25. Left Justified Data Format (24 Bit Example)
88
FIGURE 26. Right Justified Data Format (24 Bit Example)
88
FIGURE 27. PCM Serial Data Format (16 Bit Example)
88
FIGURE 28. Timing for I S Master
89
FIGURE 29. Timing for I S Slave
89
TABLE 60. BASIC_SETUP (0X50H/0X60H)
90
TABLE 61. CLK_GEN_1 (0X51H/0X61H)
90
TABLE 62. CLK_GEN_1 (0X52H/62H)
91
TABLE 63. CLK_GEN_1 (0X53H/63H)
91
TABLE 64. DATA_WIDTHS (0X54H/64H)
92
TABLE 65. RX_MODE (0X55H/X65H)
93
TABLE 66. TX_MODE (0X56H/X66H)
94
Digital Effects Engine
95
FIGURE 30. ADC DSP Effects Chain
95
FIGURE 31. DAC DSP Effects Chain
95
TABLE 67. ADC EFFECTS (0X70H)
96
TABLE 68. DAC EFFECTS (0X71H)
96
TABLE 69. HPF MODE (0X80H)
96
FIGURE 32. ALC Example
97
FIGURE 33. ALC Limiter
98
TABLE 70. ADC_ALC_1 (0X81H)
99
TABLE 71. ADC_ALC_2 (0X82H)
99
TABLE 72. ADC_ALC_3 (0X83H)
100
TABLE 73. ADC_ALC_4 (0X84H)
101
TABLE 74. ADC_ALC_5 (0X85H)
102
TABLE 75. ADC_ALC_6 (0X86H)
103
TABLE 76. ADC_ALC_7 (0X87H)
103
TABLE 77. ADC_ALC_8 (0X88H)
103
TABLE 78. ADC_L_LEVEL (0X89H)
104
TABLE 79. ADC_R_LEVEL (0X8Ah)
105
FIGURE 34. Audio Compressor Effect
106
FIGURE 35. Soft Knee Example with Compression Ratio Setting of 1:3.4
107
TABLE 80. SOFTCLIP1 (0X90H)
108
TABLE 81. SOFTCLIP2 (0X91H)
109
TABLE 82. SOFTCLIP3 (0X92H)
110
TABLE 83. DAC_ALC_1 (0Xa0H)
110
DAC Effects Registers
111
TABLE 84. DAC_ALC_2 (0Xa1H)
111
TABLE 85. DAC_ALC_3 (0Xa2H)
112
TABLE 90. DAC_ALC_8 (0Xa7H)
115
TABLE 91. DAC_L_LEVEL (0Xa8H)
116
TABLE 92. DAC_R_LEVEL (0Xa9H)
117
TABLE 93. EQ_BAND_1 (0Xabh)
118
TABLE 94. EQ_BAND_2 (0Xach)
119
TABLE 95. EQ_BAND_3 (0Xadh)
120
TABLE 96. EQ_BAND_4 (0Xaeh)
121
TABLE 97. EQ_BAND_5 (0Xafh)
122
TABLE 98. SOFTCLIP1 (0Xb0H)
123
TABLE 99. SOFTCLIP2 (0Xb1H)
124
TABLE 100. SOFTCLIP3 (0Xb2H)
125
GPIO Registers
126
TABLE 101. GPIO1 (0Xe0H)
126
TABLE 102. GPIO2 (0Xe1H)
127
TABLE 103. RESET (0Xf0H)
127
TABLE 104. Spread Spectrum (0Xf1H)
127
TABLE 105. FORCE (0Xfe)
127
Schematic Diagram
128
FIGURE 36. Demo Board Schematic
128
FIGURE 37. Demo Board Schematic
129
Demonstration Board Layout
130
FIGURE 38. Top Silkscreen
130
FIGURE 39. Top Layer
130
FIGURE 40. Inner Layer 2
131
FIGURE 41. Inner Layer 3
131
FIGURE 42. Inner Layer 4
132
FIGURE 43. Inner Layer 5
132
FIGURE 44. Bottom Layer
133
FIGURE 45. Bottom Silkscreen
133
Revision History
134
Physical Dimensions
135

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