Simplified Pga Section Of The Ths7002 - Texas Instruments THS7002 User Manual

Programmable Gain Amplifier Gain Control
Figure 1–4. Simplified PGA Section of the THS7002
No Source Impedance
V IN
R SOURCE
R TERMINATION
The PGA VREF terminals are also accessible via test points TP8 and TP14.
Typically, the DIP switches are used to keep this point at ground. If a voltage
is applied to this terminal, then the output of the PGA section will amplify the
applied reference voltage by one plus the selected gain. Thus, the output gain
due only to VREF will be from +0.6 dB to +21 dB according to the following
formula:
Typically, the output of the PGA will directly drive an A/D converter. Because
of the limited linear input range and saturation characteristics of most ADCs,
the PGA outputs incorporate a voltage clamp. Because the internal clamps
use the same clamping reference voltages, the outputs of both PGAs are
clamped to the same values. These clamps are typically connected to the
power supply pins to allow a full output range. However, by setting switch S1:F
to OFF and setting switch S2:F to ON, the outputs will be clamped to either
+Vcc or +5V (depending on JP5) and ground. The outputs can be further
limited by applying an external reference voltage to test points TP5 (VH) and
TP6 (VL). The accuracy of this clamp is dependant on the amount of current
flowing through the internal clamping diodes. As is typical with all diodes, the
voltage drop across this diode increases with current. Therefore, the accuracy
of the clamp is highly dependant upon the output voltage, the clamping voltage
differences, and the output current. The 50-
this EVM only for surge suppression. In a final system layout, these resistors
are not required for proper operation.
1-8
PGA
–V IN
R G
PGA
V REF
+ )
V
OUT
20 Log 1
10
V
REF
G 0 G 1 G 2
THS7002 IC
R F
–
PGA
+
PGA Gain(V V
series resistors are placed on
General Information
Positive
Clamp V H
PGA
V OUT
Negative
Clamp V L