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8.2.3 State_2 (AMPS ON)
Once the common mode points have settled, the amplifiers
power up with their inputs muted. Any calibration takes place
at this stage. Protection circuits enable and the I/O amplifiers
(not the analog mixer yet) are allowed to unmute once vcm
has settled, ensuring better settling of the common mode
throughout the muted mixer.
8.2.3.1 AMPLIFIER CONTROL FSM
The muting, unmuting and volume control is always handled
by a separate state machine for each amplifier. This sec-
The controller waits 1ms for this comparator to stabilize then
monitors the output of the comparator for a Zero Crossing
Event. At this exact moment the new gain or mute/unmute
condition is applied to the amplifier (in conjunction with any
changes required to the rest of the analog mixer to ensure
click and pop free operation). The comparator is then pow-
ered down. If no zero crossing occurs after 11ms (assume
audio content at frequencies above 36Hz) the changes are
applied regardless and the controller returns to a zero power
state.
The PMC leaves STATE_2 after 256 clock cycles (about
1ms).
8.2.4 State_3 (UNMUTE)
In state 3 the audio DACs and ADCs have been cleared and
are unmuted then the digital and analog mixers are unmuted.
The PMC leaves STATE_3 after 256 clock cycles (about
1ms).
8.2.5 State_4 (ON)
The PMC now sets the CHIP_ACTIVE flag (0x00h bit[7]). The
internal timers are all powered down. The ENABLE pin is
FIGURE 6. Zero Cross Detect Comparator (ZXD)
17
ondary state machine notes a change in the requested state
for each amplifier and requests a clock and a 10ms count-
down from the PMC clock domain so it can proceed to safely
change the gain of the amplifier.
The amp control FSM checks the current gain and signal
routing and if required (if zipper or click and pop is a risk) en-
ables a small differential comparator on the output of the amp.
monitored for a falling edge. Once a deglitched falling edge is
seen the FSM moves to state 5.
8.2.6 State_5 (MUTE)
The output stages are muted first using the amplifier control
FSM for each channel. The digital logic circuits are also muted
and cleared at this stage. Once the amplifiers are muted and
1ms has passed (256 clock cycles) the PMU moves to state
6. CHIP_ACTIVE is cleared at this stage.
8.2.7 State_6 (AMPS_OFF)
With the output stages muted the I/O amplifiers can be dis-
abled, only the ADCs and DACs remain enabled, flushing out
any residual data from their filters. The device waits another
256 clock cycles.
8.2.8 State_7 (OFF)
The Bias circuits are disabled and the common mode and
reference bypass points are allowed to discharge. The MCLK
and oscillator are disabled and power is leakage only.
301282i0
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