Ths7002 Evaluation Module; Ths7002 Evm Power Conditioning Schematic Diagram; Description - Texas Instruments THS7002 User Manual

Figure 1–1. THS7002 Evaluation Module
J1
+V CC
L1
1998
J6
Input A
C1
C2
U2
C3
R4
U2 Out
J7
Input B
B
Input power is applied to the EVM through banana jacks J1, J2, J3, and J4. An
LC filter on each power bus isolates the EVM circuits from the external supply
(Figure 1–2). J4 provides a reference point for numerous circuit functions and
draws relatively little current. The schematic for the EVM amplifiers appears
in Figure 1–3.
Figure 1–2. THS7002 EVM Power Conditioning Schematic Diagram
J1
V CC
L1
0.22 H
15 V
SLOP136 THS7002 EVM Board
Rev. B
J2
J3
GND
+ +
C4 C5
Pre-Amp A
Output
AG2
(3)
J5
AG1
(2)
AG0
(1)
C6
R23
C7
R25
R6
R20
1 R8
R27
R7
U1
R29
R9
R1 R2
C11
C10
R10 C12
C9
R3
R35
R12 C13
R37
R39
R41
1
C14
1
VH
JP3 JP4
1
(6)
BVREF
R16
(5)
R17
BS/D
J8
(4)
Pre-Amp B
Output
J2 J3
GND –V CC
TP1
C5
C4
6.8 F
6.8 F
+
+
J4
–V CC +5 V
+
L2 C21
C17
GND
S1
AS/D
(4)
AVREF
(5)
VL
(6)
R24
PGA – A
R26 Output
R28
R30
R32
C18
C19
R34
PGA – B
R36
Output
R38
R40
R42
S2
BG2
(1)
BG1
(2)
BG0
(3)
1
C20
JP5
J4
5 V
L2 C21
6.8 F
0.22 H
+
–15 V
5 V
General Information

Description

J9
J10
1-3