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Table 4-4. Advanced Chipset Control Submenu
Menu Item
NorthBridge Configuration
submenu
SouthBridge Configuration
submenu
Table 4-5. NorthBridge Configuration Submenu
Menu Item
Memory Configuration
Bank Interleaving
Channel
Interleaving
Enable Clock to
All Dimms
Mem Clk Tristate
C3/ALTVID
Memory Hole
Remapping
CS Sparing
DCT Unganged
Mode
Power Down
Enable
Power Down
Mode
ECC Configuration
ECC Mode
DRAM ECC
Enable
DRAM SCRUB
REDIRECT
4-Bit ECC
Mode
DRAM BG
Scrub
Data Cache BG
Scrub
Description
See
Table 4-5
See
Table 4-6
Description
Select Auto to automatically enable a bank-interleaving memory scheme when
this function is supported by the processor. The options are Auto and D
Selects the channel-interleaving memory scheme when this function is
supported by the processor. The options are D
A
B
12, XOR of Address Bits [20:16, 6] and XOR
DDRESS
ITS
[20:16, 9].
Use this setting to enable unused clocks to all DIMMSs, even if some DIMM slots
are unpopulated. Options are E
Use this setting to E
NABLE
VID.
When Enabled, this feature enables hardware memory remapping around the
memory hole. Options are Enabled and D
This setting will reserve a spare memory rank in each node when enabled.
Options are E
and Disable.
NABLE
This setting enables unganged DRAM mode (64-bit). Options are A
mode) and Always (unganged mode).
This setting enables or disables the DDR power down mode. Options are
Enabled and D
ISABLED
This sets the power down mode. Options are Channel and C
This setting affects the DRAM scrub rate based on its setting. Options are
D
, Basic, G
ISABLED
OOD
chosen, some or all of the following settings will become active:
DRAM ECC allows hardware to report and correct memory errors automatically.
Options are Enabled and D
Allows system to correct DRAM ECC errors immediately, even with background
scrubbing on. Options are Enabled and D
Allows the user to enabled 4-bit ECC mode (also known as ECC Chipkill).
Options are E
and Disabled.
NABLED
Corrects memory errors so later reads are correct. Options are Disabled and
various times in nanoseconds and microseconds.
Allows L1 cache RAM to be corrected when idle. Options are Disabled and
various times in nanoseconds and microseconds.
for further details and submenus.
for further details and submenus.
and Disabled.
NABLED
or Disable memory clock tristate during C3 and ALT
ISABLED
.
, S
, M
and U
UPER
AX
SER
.
ISABLED
ISABLED
4-5
Chapter 4: BIOS
, A
B
ISABLED
DDRESS
ITS
A
OF
DDRESS
.
UTO
S
HIP
ELECT
. Depending upon the setting
.
.
ISABLED
6,
B
ITS
(ganged
.
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