Sharp ER-A750 Service Manual page 62

14. I/O expansion bus specifications
The table below shows the standard bus for expanding optional
devices
Signal name Pin No.
GND 1
GND 2
RDO 3
WRO 4
+5V 5
+5V 6
A23 7
A22 8
A21 9
A20 10
A19 11
A18 12
A17 13
A16 14
A15 15
A14 16
A13 17
A12 18
A11 19
A10 20
A9 21
A8 22
A7 23
A6 24
A5 25
A4 26
+24V 27
+24V 28
A1 29
A0 30
RESET 31
OPTCS 32
SYNC 33
MCRRDY1 34
MCRRDY2 35
MCR1 36
MCR2 37
38
GND 39
GND 40
Table 18
Pin No. Signal name
41 GND
42 GND
43 RD
44 EXWAIT
45 BREQ
46 BACK
47 TRQ2
48 TRQ1
49 EXINT1
50 EXINT0
51 N.C.
52 IRQ1
53 RFSH
54 IPLON0
55 D7
56 D6
57 D5
58 D4
59 D3
60 D2
61 D1
62 D0
63 POFF
64 VCKDC
65 +12V
66 A3
67 +24V
68 +24V
69 A2
70 RES
71 AS
72 WR
73
74
75
76
77 –12V
78
79 GND
80 GND
15. Reset sequence
The reset sequence block diagram is shown below. Note that RESET
signal (system reset) and CKDCR signal (CKDC reset) are different
from each other.
VCC
SLIDE
SW
STOP
CPU
IRQ0
15-1. Power ON/OFF
The flow of signal processing at the time of the power supply turning
On/Off is as follows:
<Power OFF>
Power supply
1 POFF L
2
3
4
<Power ON>
Power supply
1 POFF H
2
The table below shows the timing chart.
+5V,+12V
PG GOOD
(POFF)
200ms
RESET
MIN
(System)
STOP
SHEN
SCK
7 – 32
CKDCR
(CKDC reset)
POFF
CKDC7 PG
GOOD
RESET
(System reset)
MPCA7
INT0
Fig. 14
Table 19
MPCA6 CPU
IRQ0 L
STOP L
(System reset)
Table 20
MPCA6 CPU
RESET
(System reset)
10ms MIN
20ms is assured when as power is off.
8 PULSE
Fig. 15
POWER
SUPPLY
CKDC7
RESET L
CKDC7
H