Sharp ER-A750 Service Manual page 43

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2-4. USART (MB89371A)
1) General
The MB89371A (Serial data transmitter/receiver, 2 units) is a versa-
tile-use interface LSI for communication lines, which is equipped
with two sets of equivalent units of the MB89251A (serial data trans-
mitter/receiver), the baud rate generating section, and the interrup-
tion adjustment section.
It is positioned between the line Modem and the computer, and
used for serial/parallel conversion of data, data send/receive opera-
tion check, and the synchronization mode selection according to the
program assignment.
The transmitter section converts parallel data into serial data, and
adds the parity bit, the start bit, and the stop bit to them, and
transmits them. In the synchronization mode, it transmits synchroni-
zation characters during no transmission data period. In the ad-
vancement synchronization mode, it allows selection of transmission
clocks and transmission baud rates.
The receiving section converts serial data into parallel data, and
checks parities to judge that data are properly transmitted.
In the synchronization mode, it detects synchronization characters
and makes synchronization of transmission/reception operations
with the transmitter side. In the advancement synchronization mode,
it allows selection of transmission clocks and reception baud rates.
The baud rate generating section generates clock pulse signals
which are used in transmission and reception and delivered through
the baud rate selecting section to the SDTR section.
It provides the loop back diagnostic function which crosses interface
lines of the Modem and loops transmission and reception signals,
facilitating the operation check.
Features
Two independent channels of SDTR.
Built-in baud rate generator which allows setting for each channel
External clock available
Internal clock output available.
Maskable interruption generating circuit
Two channels are assigned to different address spaces.
Baud rate DC ~ 240K baud (with external clocks)
Full duplex communication
Program assignment in synchronization mode
Data bit length: 5 - 8 bits
Character synchronization system: Internal synchronization,
external synchronization
Number of synchronized characters: Single character, double
characters
Parity occurrence and check: parity valid/invalid
Operations in the synchronization mode
Overrun error and parity error detection
Transmit/receive buffer state acknowledgment
Synchronization character detection
Automatic insertion of synchronization character
Program assignment function in the advancement synchroniza-
tion mode
Data bit length: 5 ~ 8 bits
Stop bit length: 1, 1
, 2 bits
1 2
Baud rate: Transmission clock, reception clock x 1, x 1/16, x
1/64
Parity occurrence and check: Parity valid, invalid
even parity, odd parity
Even parity, odd parity
Operations in the advancement synchronization mode
Detection of framing error, overrun error, parity error
Transmission/reception buffer state acknowledgment
Break characters detection
Error start bit detection
IBM Bi-sync system operation allowed.
Duplex buffer system in the transmission and the reception sec-
tions.
Loop back diagnostic functions
I/O signal level TTL compatible
Compatible with standard microprocessor in connecting pins and
signal timing.
Standard 42 pin plastic DIP, 48 pin plastic QFP
+5V single power source
2) Pin configuration
DB4
1
DB5
2
DB6
3
DB7
4
TRNCLK1
5
W
6
CS1
7
RSLCT0
8
R
9
RCVRDY1
10
RSLCT1
11
CS2
12
3) Block diagram
DB0~DB7
CS1,CS2
RSLCT0,RSLCT1
W,R
TRNRDY1
RCVRDY1
SYNC,BRK1
Mode setting
TRNEMP1
register 1
RST
TRNRDY2
RCVRDY2
SYNC/BRK2
TRNEMP2
CLOCK
7 – 13
36
RTS1
35
DSR1
34
RST
33
CLOCK
32
TRNDT1
31
TRNEMP1/ST1-1
30
CTS1
29
SYNC/BRK1
28
TRNRDY1
27
RCVCLK2
26
DTR2
25
RTS2
Address
decoder
SDTR1
Interrup-
tion
mask 1
Baud rate
Clock
setting
control
register 1
1
Baud rate
generator
SDTR2
Interrup-
tion
Mode setting
mask 2
register 2
Baud rate
Clock
setting
control
register 2
2
VCC
GND
TRNDT1
Loop
RTS1
back
DTR1
control
RCVDT1
1
CTS1
DSR1
TRNCLK1
RCVCLK1
TRNDT2
Loop
RTS2
back
DTR2
control
RCVDT2
2
CTS2
DSR2
TRNCLK2
RCVCLK2

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