Toshiba TECRA M10 Maintenance Manual page 76

2 Troubleshooting Procedures
System BIOS IRT processing
F100 CPU setup
Initialization of ICH, MCH, and
Super I/O
setup of SD controller
F101
setup of PIT
Memory initialization
Memory error
F102 setup for using RAM area
check memory error of RAM area
memory error
CPU setup
F103
CMOS setup
CMOS error
Resume branch
BIOS processing reading
F104
ROM read error
F105 check of BIOS processing
RAM setup
F106
Initialization of ICH (APIC)
Initialization of ICH (PIT)
PIT initialization error
CPU check
check of ROM data
SMI setup
F107
Part number data distinction
Panel distinction
CMOS check
Clock generator setup
CPU initialization
2-24 [CONFIDENTIAL]
Table 2-5 Debug port error status (2/8)
CPU
ICH(PCI register,
PIT controller)
MCH(PCI register )
card controller
BIOSROM
Super I/O
MCH(PCI register)
RAM(SPD, memory)
ICH(PCI register,
CMOS)
CPU
BIOSROM
CPU
ICH(CMOS)
BIOSROM
ICH(CMOS)
BIOSROM
RAM
EC/KBC(EC), TPM,
CPU
CPU
ICH(CMOS,PIC
controller, I/O, MEM
I/O)
RAM
CPU
ICH(PIT controller,
MEM I/O, CMOS,I/O)
Clock generator,
EC/KBC(EC),
BIOSROM
Panel(EEPROM)
2.4 System Board Troubleshooting
IS1050 (CPU Socket)
IS1050 (CPU Socket)
IC1200 (MCH)
IC1600 (ICH)
IC2000 (SD Cont.)
IC3000 (BIOS ROM)
IC3400 (Super I/O)
IC1200 (MCH)
CN1400 (RAM Conn.)
CN1410 (RAM Conn.)
IC1600 (ICH)
IS1050 (CPU Socket)
IC3000 (BIOS ROM)
IS1050 (CPU Socket)
IC1600 (ICH)
IC3000 (BIOS ROM)
CN1400 (RAM Conn.)
CN1410 (RAM Conn.)
IC1600 (ICH)
IC3000 (BIOS ROM)
IC3300 (TPM)
IC3200 (EC/KBC)
IC3200(EEPROM)
IS1050 (CPU Socket)
IS1050 (CPU Socket)
CN1400 (RAM Conn.)
CN1410 (RAM Conn.)
IC1600 (ICH)
IC1000 (CLKGEN)
IS1050 (CPU Socket)
IC1600 (ICH)
IC3000 (BIOS ROM)
IC3200 (EC/KBC)
CN5000 (LCD Conn.)
TECRA M10 Maintenance Manual (960-685)