SOYO SY-5SSM User's Manual & Technical Reference page 53

BIOS Setup Utility
CHIPSET FEATURES SETUP
CHIPSET
FEATURES
Ref/Act
Command Delay
Refresh Queue
Depth
RAS Precharge
Time
RAS to CAS
Delay
CPU to PCI Burst
Mom. WR
CPU to PCI Post
Write
Setting Description
6T Set the DRAM clock of the
5T,7T, 8T refresh command to
refresh/active command
delay.
12 Set the depth of refresh
0, 4, 8, queue.
3T The precharge time is the
2T, 4T, 5T number of cycles it takes for
the RAS to accumulate its
charge before DRAM
refreshes. If insufficient time
is allowed, refresh may be
incomplete and the DRAM
may fail to retain data.
3T When DRAM is refreshed,
2T,4T,5T both rows and columns are
addressed separately. This
setup item allows you to
determine the timing of the
transition from RAS (row
address strobe) to CAS
(column address strobe).
Disabled Select enabled permits PCI
burst memory write cycles,
Enabled
for faster performance.
When disabled,
performance is slightly
slower, but more reliable.
Disabled Select enabled to use a fast
buffer for posting writes to
Enabled
memory. Using a fast
buffer releases the CPU
before completion of a write
cycle to DRAM.
49
SY-5SSM & SY-5SSM/5 V1.1
Note
Default
Default
Default
Default
Default
Default