“Important Alert Items” in this manual. Keep this manual handy, and keep it carefully. FUJITSU makes every effort to prevent users and bystanders from being injured or from suffering damage to their property. Use the product according to this manual.
Revision History (1/1) Edition Date Revised section (*1) Details (Added/Deleted/Altered) 1997-07-15 — — *1 Section(s) with asterisk (*) refer to the previous edition when those were deleted. C141-E042-01EN...
Preface This manual describes the MHA2021AT and MHA2032AT, 2.5-inch hard disk drives. These drives have a built-in controller that is compatible with the ATA interface. This manual describes the specifications and functions of the drives and explains in detail how to incorporate the drives into user systems. This manual assumes that the reader has a basic knowledge of hard disk drives and their implementations in computer systems.
Preface Abbreviation This section gives the meanings of the definitions used in this manual. Conventions for Alert Messages This manual uses the following conventions to show the alert messages. An alert message consists of an alert signal and alert statements. The alert signal consists of an alert symbol and a signal word or just a signal word.
“Disk drive defects” refers to defects that involve adjustment, repair, or replacement. Fujitsu is not liable for any other disk drive defects, such as those caused by user misoperation or mishandling, inappropriate operating environments, defects in the power supply or cable, problems of the host system, or other causes outside the disk drive.
Important Alert Items Important Alert Messages The important alert messages in this manual are as follows: A hazardous situation could result in minor or moderate personal injury if the user does not perform the procedure correctly. Also, damage to the predate or other property, may occur if the user does not perform the procedure correctly.
Contents 4.6.3 Read circuit 4-12 4.6.4 Time base generator circuit 4-13 Servo Control 4-14 4.7.1 Servo control circuit 4-14 4.7.2 Data-surface servo format 4-18 4.7.3 Servo frame format 4-18 4.7.4 Actuator motor control 4-19 4.7.5 Spindle motor control 4-20 CHAPTER 5 Interface ..................
Contents CHAPTER 6 Operations..................6-1 Device Response to the Reset 6.1.1 Response to power-on 6.1.2 Response to hardware reset 6.1.3 Response to software reset 6.1.4 Response to diagnostic command Address Translation 6.2.1 Default parameters 6.2.2 Logical address Power Save 6.3.1 Power save mode 6.3.2 Power commands 6-11...
Contents Illustrations Figures Figure 1.1 Current fluctuation (Typ.) at +5V when power is turned on Figure 2.1 Disk drive outerview Figure 2.2 Configuration of disk media heads Figure 2.3 1 drive system configuration Figure 2.4 2 drives configuration Figure 3.1 Dimensions Figure 3.2 Orientation Figure 3.3 Mounting frame structure Figure 3.4 Surface temperature measurement points...
Contents Figure 5.6 Protocol for the command execution without data transfer 5-73 Figure 5.7 Normal DMA data transfer 5-75 Figure 5.8 Data transfer timing 5-77 Figure 5.9 Single word DMA data transfer timing (mode 2) 5-78 Figure 5.10 Multiword DMA data transfer timing (mode 2) 5-79 Figure 5.11 Power on Reset Timing 5-80...
Contents Table 5.10 Contents of security password 5-59 Table 5.11 Contents of SECURITY SET PASSWORD data 5-64 Table 5.12 Relationship between combination of Identifier and Security level, and operation of the lock function 5-65 Table 5.13 Command code and parameters 5-67 Table 6.1 Default parameters...
CHAPTER 1 Device Overview Features Device Specifications Power Requirements Environment Specifications Acoustic Noise Shock and Vibration Reliability Error Rate Media Defects Overview and features are described in this chapter, and specifications and power requirement are described. The MHA2021AT and MHA2032AT are 2.5-inch hard disk drives with built-in disk controllers.
Device Overview 1.1 Features 1.1.1 Functions and performance (1) Compact The disk has 1 or 2 disks of 65 mm (2.5 inches) diameter, and its height is 12.5 mm (0.492 inch). (2) Large capacity The disk drive can record up to 1,083 MB (formatted) on one disk using the (8/9) PRML recording method and 13 recording zone technology.
1.1 Features (2) 128-KB data buffer The disk drive uses a 128-KB data buffer to transfer data between the host and the disk media. In combination with the read-ahead cache system described in item (3) and the write cache described in item (7), the buffer contributes to efficient I/O processing.
Device Overview 1.2 Device Specifications 1.2.1 Specifications summary Table 1.1 shows the specfications of the disk drive. Table 1.1 Specifications MHA2021AT MHA2032AT Format Capacity (*1) 2.16 GB 3.25 GB Number of Heads Number of Cylinders (User) 6,372 Bytes per Sector Recording Method (8/9) PRML Track Density...
1.3 Power Requirements Capacity under the LBA mode. Under the CHS mode (normal BIOS specification), formatted capacity, number of cylinders, number of heads, and number of sectors are as follows. Model Formatted Capacity No. of Cylinder No. of Heads No. of Sectors MHA2021AT 2,167.60 MB 4,200...
Device Overview (3) Current Requirements and Power Dissipation Table 1.3 lists the current and power dissipation. Table 1.3 Current and power dissipation Typical RMS Current Typical Power (*2) Spin up (*1) 1.0 A Watts 5.0 W Idle 0.236 A T.B.D T.B.D 1.18 W R/W (*3) 0.5 A T.B.D...
1.9 Media Defects (3) Service life In situations where management and handling are correct, the disk drive requires no overhaul for five years when the DE surface temperature is less than 48°C. When the DE surface temperature exceeds 48°C, the disk drives requires no overhaul for five years or 20,000 hours of operation, whichever occurs first.
CHAPTER 2 Device Configuration Device Configuration System Configuration This chapter describes the internal configurations of the hard disk drives and the configuration of the systems in which they operate. C141-E042-01EN...
Device Configuration 2.1 Device Configuration Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE), read/write preamplifier, and controller PCA. The disk enclosure contains the disk media, heads, spindle motors, actuators, and a circulating air filter. Figure 2.1 Disk drive outerview (1) Disk The outer diameter of the disk is 65 mm.
2.1 Device Configuration Head Head MHA2021AT MHA2032AT Figure 2.2 Configuration of disk media heads (3) Spindle motor The disks are rotated by a direct drive Hall-less DC motor. (4) Actuator The actuator uses a revolving voice coil motor (VCM) structure which consumes low power and generates very little heat.
Device Configuration (5) Air circulation system The disk enclosure (DE) is sealed to prevent dust and dirt from entering. The disk enclosure features a closed loop air circulation system that relies on the blower effect of the rotating disk. This system continuously circulates the air through the circulation filter to maintain the cleanliness of the air within the disk enclosure.
2.2 System Configuration 2.2.3 2 drives connection MHA2021AT (Host adaptor) MHA2032AT MHA2021AT MHA2032AT Note: When the drive that is not conformed to ATA is connected to the disk drive above configuration, the operation is not guaranteed. Figure 2.4 2 drives configuration HA (host adaptor) consists of address decoder, driver, and receiver.
CHAPTER 3 Installation Conditions Dimensions Mounting Cable Connections Jumper Settings This chapter gives the external dimensions, installation conditions, surface temperature conditions, cable connections, and switch settings of the hard disk drives. C141-E042-01EN...
Installation Conditions 3.1 Dimensions Figure 3.1 illustrates the dimensions of the disk drive and positions of the mounting screw holes. All dimensions are in mm. Figure 3.1 Dimensions C141-E042-01EN...
Installation Conditions (2) Frame The MR head bias of the HDD disk enclosure (DE) is zero. The mounting frame is connected to SG. Use M3 screw for the mounting screw and the screw length should satisfy the specification in Figure 3.3. The tightening torque must not exceed 3 kgcm.
3.2 Mounting (4) Ambient temperature The temperature conditions for a disk drive mounted in a cabinet refer to the ambient temperature at a point 3 cm from the disk drive. The ambient temperature must satisfy the temperature conditions described in Section 1.4, and the airflow must be considered to prevent the DE surface temperature from exceeding 60 C.
Installation Conditions (5) Service area Figure 3.5 shows how the drive must be accessed (service areas) during and after installation. Mounting screw hole Cable connection Mounting screw hole Figure 3.5 Service area (6) External magnetic fields Data corruption: Avoid mounting the disk drive near strong magnetic sources such as loud speakers.
3.3 Cable Connections 3.3 Cable Connections 3.3.1 Device connector The disk drive has the connectors and terminals listed below for connecting external devices. Figure 3.6 shows the locations of these connectors and terminals. Connector, setting pins Figure 3.6 Connector locations C141-E042-01EN...
Installation Conditions 3.3.2 Cable connector specifications Table 3.2 lists the recommended specifications for the cable connectors. Table 3.2 Cable connector specifications Name Model Manufacturer Cable socket 89361-144 BERG ATA interface and (44-pin type) power supply cable (44-pin type) Cable FV08-A440 Junkosha (44-pin type) For the host interface cable, use a ribbon cable.
3.4 Jumper Settings 3.3.4 Power supply connector (CN1) Figure 3.8 shows the pin assignment of the power supply connector (CN1). Figure 3.8 Power supply connector pins (CN1) 3.4 Jumper Settings 3.4.1 Location of setting jumpers Figure 3.9 shows the location of the jumpers to select drive configuration and functions.
Installation Conditions 3.4.2 Factory default setting Figure 3.10 shows the default setting position at the factory. Figure 3.10 Factory default setting 3.4.3 Master drive-slave drive setting Master device (device #0) or slave device (device #1) is selected. Figure 3.11 Jumper setting of master or slave device Note: Pins A and C should be open.
3.4 Jumper Settings 3.4.4 CSEL setting Figure 3.12 shows the cable select (CSEL) setting. Note: The CSEL setting is not depended on setting between pins Band D. Figure 3.12 CSEL setting Figure 3.13 and 3.14 show examples of cable selection using unique interface cables.
CHAPTER 4 Theory of Device Operation Outline Subassemblies Circuit Configuration Power-on sequence Self-calibration Read/Write circuit Servo Control This chapter explains basic design concepts of the disk drive. Also, this chapter explains subassemblies of the disk drive, each sequence, servo control, and electrical circuit blocks.
Theory of Device Operation 4.1 Outline This chapter consists of two parts. First part (Section 4.2) explains mechanical assemblies of the disk drive. Second part (Sections 4.3 through 4.7) explains a servo information recorded in the disk drive and drive control method. 4.2 Subassemblies The disk drive consists of a disk enclosure (DE) and printed circuit assembly (PCA).
4.2 Subassemblies Head Head MHA2021AT MHA2032AT Figure 4.1 Head structure 4.2.3 Spindle The spindle consists of a disk stack assembly and spindle motor. The disk stack assembly is activated by the direct drive sensor-less DC spindle motor, which has a speed of 4,000 rpm 1%. The spindle is controlled with detecting a PHASE signal generated by counter electromotive voltage of the spindle motor at starting.
Theory of Device Operation 4.3 Circuit Configuration Figure 4.2 shows the disk drive circuit configuration. (1) Read/write circuit The read/write circuit consists of two LSIs; read/write preamplifier (PreAMP) and read channel (RDC). The PreAMP consists of the write current switch circuit, that flows the write current to the head coil, and the voltage amplifier circuit, that amplitudes the read output from the head.
Theory of Device Operation 4.4 Power-on Sequence Figure 4.3 describes the operation sequence of the disk drive at power-on. The outline is described below. a) After the power is turned on, the disk drive executes the MPU bus test, internal register read/write test, and work RAM read/write test. When the self-diagnosis terminates successfully, the disk drive starts the spindle motor.
4.5 Self-calibration Figure 4.3 Power-on operation sequence 4.5 Self-calibration The disk drive occasionally performs self-calibration in order to sense and calibrate mechanical external forces on the actuator, and VCM tarque. This enables precise seek and read/write operations. 4.5.1 Self-calibration contents (1) Sensing and compensating for external forces The actuator suffers from torque due to the FPC forces and winds accompanying disk revolution.
Theory of Device Operation The forces are compensated by adding the measured value to the specified current value to the power amplifier. This makes the stable servo control. To compensate torque varing by the cylinder, the disk is divided into 8 areas from the innermost to the outermost circumference and the compensating value is measured at the measuring cylinder on each area at factory calibration.
4.6 Read/write Circuit Table 4.1 Self-calibration execution timechart Time elapsed Time elapsed (accumulated) At power-on Initial calibration About 5 minutes About 5 minutes About 5 minutes About 10 minutes About 10 minutes About 20 minutes About 10 minutes About 30 minutes About 15 minutes About 45 minutes About 15 minutes...
Theory of Device Operation signal (WUS) when a write error occurs due to head short-circuit or head disconnection. 4.6.2 Write circuit The write data is output from the hard disk controller (HDC) with the NRZ data format, and sent to the encoder circuit in the RDC with synchronizing with the write clock.
Theory of Device Operation 4.6.3 Read circuit The head read signal from the PreAMP is regulated by the automatic gain control (AGC) circuit. Then the output is converted into the sampled read data pulse by the programmable filter circuit and the adaptive equalizer circuit. This clock signal is converted into the NRZ data by the 8/9 GCR decoder circuit based on the read data maximum-likelihood-detected by the Viterbi detection circuit, then is sent to the HDC.
4.6 Read/write Circuit (4) Viterbi detection circuit The sample hold waveform output from the adaptive equalizer circuit is sent to the Viterbi detection circuit. The Viterbi detection circuit demodulates data according to the survivor path sequence. (5) Data separator circuit The data separator circuit generates clocks in synchronization with the output of the adaptive equalizer circuit.
Theory of Device Operation 4.7 Servo Control The actuator motor and the spindle motor are submitted to servo control. The actuator motor is controlled for moving and positioning the head to the track containing the desired data. To turn the disk at a constant velocity, the actuator motor is controlled according to the servo data that is written on the data side beforehand.
4.7 Servo Control The major internal operations are listed below. Spindle motor start Starts the spindle motor and accelerates it to normal speed when power is applied. b. Move head to reference cylinder Drives the VCM to position the head at the any cylinder in the data area. The logical initial cylinder is at the outermost circumference (cylinder 0).
4.7 Servo Control (2) Servo burst capture circuit The servo burst capture circuit reproduces signals (position signals) that indicate the head position from the servo data on the data surface. SERVO A, SERVO B, SERVO C and SERVO D burst signals shown in Figure 4.8 followed the servo mark, cylinder gray and index information are output from the servo area on the data surface via the data head.
Theory of Device Operation 4.7.2 Data-surface servo format Figure 4.7 describes the physical layout of the servo frame. The three areas indicated by (1) to (3) in Figure 4.7 are described below. (1) Inner guard band The head is in contact with the disk in this space when the spindle starts turning or stops, and the rotational speed of the spindle can be controlled on this cylinder area for head moving.
4.7 Servo Control (1) Write/read recovery This area is used to absorb the write/read transient and to stabilize the AGC. (2) Servo mark This area gererates a timing for demodulating the gray code and position- demodulating the servo A to D by detecting the servo mark. (3) Gray code (including index bit) This area is used as cylinder address.
(called SVC hereafter). The firmware operates on the MPU manufactured by Fujitsu. The spindle motor is controlled by sending several signals from the MPU to the SVC. There are three modes for the spindle control; start mode, acceleration mode, and stable rotation mode.
4.7 Servo Control d) During phase switching, the spindle motor starts rotating in low speed, and generates a counter electromotive force. The SVC detects this counter electromotive force and reports to the MPU using a PHASE signal for speed detection. e) The MPU is waiting for a PHASE signal.
Interface 5.1 Physical Interface 5.1.1 Interface signals Figure 5.1 shows the interface signals. Figure 5.1 Interface signals 5.1.2 Signal assignment on the connector Table 5.1 shows the signal assignment on the interface connector. C141-E042-01EN...
Interface [signal] [I/O] [Description] MSTR MSTR, I, Master/slave setting 1: Master 0: Slave RESET- Reset signal from the host. This signal is low active and is asserted for a minimum of 25 ms during power on. DATA 0-15 Sixteen-bit bi-directional data bus between the host and the device.
5.1 Physical Interface [signal] [I/O] [Description] PIDAG- This signal is an input mode for the master device and an output mode for the slave device in a daisy chain configuration. This signal indicates that the slave device has been completed self diagnostics.
Interface 5.2 Logical Interface The device can operate for command execution in either address-specified mode; cylinder-head-sector (CHS) or Logical block address (LBA) mode. The IDENTIFY DEVICE information indicates whether the device supports the LBA mode. When the host system specifies the LBA mode by setting bit 6 in the Device/Head register to 1, HS3 to HS0 bits of the Device/Head register indicates the head No.
Interface 5.2.2 Command block registers (1) Data register (X’1F0’) The Data register is a 16-bit register for data block transfer between the device and the host system. Data transfer mode is PIO or LBA mode. (2) Error register (X’1F1’) The Error register indicates the status of the command executed by the device. The contents of this register are valid when the ERR bit of the Status register is 1.
5.2 Logical Interface [Diagnostic code] X’01’: No Error Detected. X’02’: HDC Register Compare Error X’03’: Data Buffer Compare Error. X’05’: ROM Sum Check Error. X’80’: Device 1 (slave device) Failed. Error register of the master device is valid under two devices (master and slave) configuration.
Interface (6) Cylinder Low register (X’1F4’) The contents of this register indicates low-order 8 bits of the starting cylinder address for any disk-access. At the end of a command, the contents of this register are updated to the current cylinder number. Under the LBA mode, this register indcates LBA bits 15 to 8.
5.2 Logical Interface (9) Status register (X’1F7’) The contents of this register indicate the status of the device. The contents of this register are updated at the completion of each command. When the BSY bit is cleared, other bits in this register should be validated within 400 ns. When the BSY bit is 1, other bits of this register are invalid.
Interface - Bit 5: The Device Write Fault (DF) bit. This bit indicates that a device fault (write fault) condition has been detected. If a write fault is detected during command execution, this bit is latched and retained until the device accepts the next command or reset.
5.3 Host Commands 5.2.3 Control block registers (1) Alternate Status register (X’3F6’) The Alternate Status register contains the same information as the Status register of the command block register. The only difference from the Status register is that a read of this register does not imply Interrupt Acknowledge and INTRQ signal is not reset.
Interface When the BSY bit is 1 or the DRQ bit is 1 (the device is requesting the data transfer) and the host system writes to the command register, the correct device operation is not guaranteed. 5.3.1 Command code and parameters Table 5.3 lists the supported commands, command code and the registers that needed parameters are written.
Interface Necessary to set parameters under the LBA mode. Not necessary to set parameters (The parameter is ignored if it is set.) May set parameters The device parameter is valid, and the head parameter is ignored. The command is addressed to the master device, but both the master device and the slave device execute it.
5.3 Host Commands CM: Command register FR: Features register DH: Device/Head register ST: Status register CH: Cylinder High register ER: Error register CL: Cylinder Low register L: LBA (logical block address) setting bit SN: Sector Number register DV: Device address. bit SC: Sector Count register x, xx: Do not care (no necessary to set) Note:...
Interface Command block registers contain the cylinder, the head, and the sector addresses of the sector (in the CHS mode) or the logical block address (in the LBA mode) where the error occurred, and remaining number of sectors of which data was not transferred.
5.3 Host Commands The implementation of the READ MULTIPLE command is identical to that of the READ SECTOR(S) command except that the number of sectors is specified by the SET MULTIPLE MODE command are transferred without intervening interrupts. In the READ MULTIPLE command operation, the DRQ bit of the Status register is set only at the start of the data block, and is not set on each sector.
5.3 Host Commands (3) READ DMA (X’C8’ or X’C9’) This command operates similarly to the READ SECTOR(S) command except for following events. The data transfer starts at the timing of DMARQ signal assertion. The device controls the assertion or negation timing of the DMARQ signal. The device posts a status as the result of command execution only once at completion of the data transfer.
Interface At command completion (I/O registers contents to be read) (ST) Status information (DH) End head No. /LBA [MSB] (CH) End cylinder No. [MSB] / LBA (CL) End cylinder No. [LSB] / LBA (SN) End sector No. / LBA [LSB] (SC) 00 (*1) (ER)
Interface The data stored in the buffer, and CRC code and ECC bytes are written to the data field of the corresponding sector(s). Upon the completion of the command execution, the command block registers contain the cylinder, head, and sector addresses of the last sector written.
5.3 Host Commands (6) WRITE MULTIPLE (X’C5’) This command is similar to the WRITE SECTOR(S) command. The device does not generate interrupts (assertion of the INTRQ) signal) on each sector but on the transfer of a block which contains the number of sectors for which the number is defined by the SET MULTIPLE MODE command.
5.3 Host Commands A host system can select the following transfer mode using the SET FEATURES command. 1) Single word DMA transfer mode 0 to 2 2) Multiword DMA transfer mode 0 to 2 At command issuance (I/O registers setting contents) (CM) (DH) Start head No.
5.3 Host Commands At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information Note: Also executable in LBA mode. (10) SEEK (X’7x’, x : X’0’...
5.3 Host Commands At command issuance (I/O registers setting contents) (CM) (DH) Max. head No. (CH) (CL) (SN) (SC) Number of sectors/track (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) Max. head No. (CH) (CL) (SN) (SC)
Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information Table 5.4 Information to be read by IDENTIFY DEVICE command (1 of 3) Word Value Description...
5.3 Host Commands Word Value Description X’0000’ Undefined X’0004’ Number of ECC bytes transferred at READ LONG or WRITE LONG command 23-26 – Firmware revision (ASCII code) *3 27-46 – Model name (ASCII code) *4 X’8020’ Maximum number of sectors per interrupt on READ/WRITE MULTIPLE command X’0000’...
Interface Word Value Description X’0000’ Minor version number (not reported) X’000B’ Support of command sets *12 X’4000’ Support of command sets (fixed) 84-87 X’00’ Reserved X’0000’ Ultra DMA transfer mode *13 89-127 X’00’ Reserved (Variable) Security status *13 129-159 X’00’ Undefined 160-255 X’00’...
5.3 Host Commands *4 Word 27-46: Model name; ASCII code (40 characters, Left-justified), remainder filled with blank code (X’20’) One of two model names; MHA2021AT or MHA2032AT *5 Word 49: Capabilities Bit 15-14: Reserved Bit 13: Standby timer value. Factory default is 0. Bit 12: Reserved Bit 11:...
Interface Table 5.4 Information to be read by IDENTIFY DEVICE COMMAND (3 of 3) *9 Word 63: Multiword DMA transfer mode Bit 15-8: Currently used multiword DMA transfer mode Bit 7-0: Supportable multiword DMA transfer mode Bit 2=1 Mode 2 Bit 1=1 Mode 1 Bit 0=1 Mode 0 *10 Word 64: Advance PIO transfer mode support status...
5.3 Host Commands Bit 0 = 1 Mode 0 *14 WORD 128 Bit 15-9: Reserved Bit 8: Security level. 0: High, 1: Maximum Bit 7-5: Reserved Bit 4: 1: Security counter expired Bit 3: 1: Security frozen Bit 2: 1: Security locked Bit 1: 1: Security enabled Bit 0:...
Interface (14) SET FEATURES (X’EF’) The host system issues the SET FEATURES command to set parameters in the Features register for the purpose of changing the device features to be executed. For the transfer mode (Feature register = 03), detail setting can be done using the Sector Count register.
5.3 Host Commands At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) xx or transfer mode (FR) [See Table 5.6] At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information...
5.3 Host Commands At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) Sector count/block (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) Sector count/block (ER) Error information After power-on or after hardware reset, the READ MULTIPLE and WRITE MULTIPLE command operation are disabled as the default mode.
Interface Word 47 Bit 7-0 = 20: Maximum number of sectors that can be transferred per interrupt by the READ MULTIPLE and WRITE MULTIPLE commands are 32 (fixed). Word 59 = 0000: The READ MULTIPLE and WRITE MULTIPLE commands are disabled.
5.3 Host Commands Table 5.6 Diagnostic code Code Result of diagnostic X’01’ No error detected. X’03’ Data buffer compare error X’05’ ROM sum check error X’8x’ Failure of device 1 attention: The device responds normally to this command without excuting internal diagnostic test.
Interface command is used for checking ECC function by combining with the WRITE LONG command. Number of ECC bytes to be transferred is fixed to 4 bytes and cannot be changed by the SET FEATURES command. The READ LONG command supports only single sector operation. At command issuance (I/O registers setting contents) (CM) (DH)
5.3 Host Commands This command is operated under the following conditions: The command is issued in a sequence of the READ LONG or WRITE LONG (to the same address) command issuance. (WRITE LONG command can be continuously issued after the READ LONG command.) If above condition is not satisfied, the command operation is not guaranteed.
Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (20) WRITE BUFFER (X’E8’) The host system can overwrite the contents of the sector buffer of the device with a desired data pattern by issuing this command.
5.3 Host Commands At command issuance (I/O registers setting contents) (CM) (DH) ´ (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (21) IDLE (X’97’ or X’E3’) Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode.
Interface Sector Count register value Point of timer [X’00’] 30 minutes 1 to 3 [X’01’ to X’03’] 15 seconds 4 to 240 [X’04’ to X’F0’] (Value 5) seconds 241 to 251 [X’F1’ to X’FB’] 30 minutes [X’FC’] 21 minutes [X’FD’] 30 minutes 254 to 255 [X’FE’...
5.3 Host Commands (22) IDLE IMMEDIATE (X’95’ or X’E1’) Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. This command does not support the automatic power-down function. At command issuance (I/O registers setting contents) (CM) X’95’...
Interface Under the standby mode, the spindle motor is stopped. Thus, when the command involving a seek such as the READ SECTOR(s) command is received, the device processes the command after driving the spindle motor. attention: The automatic power-down is excuted if no command is coming for 30 min.
Interface At command issuance (I/O registers setting contents) (CM) X’99’ or X’E6’ (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (26) CHECK POWER MODE (X’98’ or X’E5’) The host checks the power mode of the device with this command.
Interface Table 5.7 Features Register values (subcommands) and functions Features Resister Function X’D0’ SMART Read Attribute Values: A device that received this subcommand asserts the BSY bit and saves all the updated attribute values. The device then clears the BSY bit and transfers 512-byte attribute value information to the host.
5.3 Host Commands Features Resister Function X’DA’ SMART Return Status: When the device receives this subcommand, it asserts the BSY bit and saves the current device attribute values. Then the device compares the device attribute values with insurance failure threshold values. If there is an attribute value exceeding the threshold, F4h and 2Ch are loaded into the CL and CH registers.
Interface At command completion (I-O registers setting contents) (ST) Status information (DH) (CH) Key-failure prediction status (C2h-2Ch) (CL) Key-failure prediction status (4Fh-F4h) (SN) (SC) (ER) Error information The attribute value information is 512-byte data; the format of this data is shown below.
5.3 Host Commands Table 5.9 Format of insurance failure threshold value data Byte Item Data format version number Attribute 1 Attribute ID Insurance failure threshold 04 to 0D Threshold 1 Reserved (Threshold of attribute 1) 0E to 169 Threshold 2 to (The format of each threshold value is the same threshold 30 as that of bytes 02 to 0D.)
Interface Attribute Attribute name Number of retries made to activate the spindle motor Number of power-on-power-off times 13 to 199 (Reserved) Write error rate 201 to 255 (Unique to vendor) Status flag Bit 0: If this bit is 1, the attribute is within the insurance range of the device when the attribute exceeds the threshold.
5.3 Host Commands The limit of a varying attribute value. The host compares the attribute values with the thresholds to identify a failure. (28) SECURITY DISABLE PASSWORD (F6h) This command invalidates the user password already set and releases the lock function.
Interface At command issuance (I-O register contents)) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O register contents) (CM) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (29) SECURITY ERASE PREPARE (F3h) The SECURITY ERASE UNIT command feature is enabled by issuing the SECURITY ERASE PREPARE command and then the SECURITY ERASE UNIT command.
5.3 Host Commands At command issuance (I-O register contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O register contents) (CM) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (30) SECURITY ERASE UNIT (F4h) This command erases all user data. This command also invalidates the user password and releases the lock function.
Interface At command issuance (I-O register contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O register contents) (CM) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (31) ECURITY FREEZE LOCK (F5h) This command puts the device into FROZEN MODE. The following commands used to change the lock function return the Aborted Command error if the device is in FROZEN MODE.
Interface (32) SECURITY SET PASSWORD (F1h) This command enables a user password or master password to be set. The host transfers the 512-byte data shown in Table 1.2 to the device. The device determines the operation of the lock function according to the specifications of the Identifier bit and Security level bit in the transferred data.
5.3 Host Commands Table 5.12 Relationship between combination of Identifier and Security level, and operation of the lock function Indentifier Level Description User High The specified password is saved as a new user password. The lock function is enabled after the device is turned off and then on.
Interface (33) SECURITY UNLOCK (F2h) This command cancels LOCKED MODE. The host transfers the 512-byte data shown in Table 1.1 to the device. Operation of the device varies as follows depending on whether the host specifies the master password or user password. When the master password is selected When the security level in LOCKED MODE is high, the password is compared with the master password already set.
5.3 Host Commands At command completion (I-O register contents) (CM) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information 5.3.3 Error posting Table 5.7 lists the defined errors that are valid for each command. Table 5.13 Command code and parameters (1 of 2) Command name Error register (X’1F1’) Status register (X’1F7’)
Interface Table 5.13 Command code and parameters (2 of 2) Command name Error register (X’1F1’) Status register (X’1F7’) INDF ABRT TK0NF DRDY CORR SET FEATURES SET MULTIPLE MODE EXECUTE DEVICE DIAGNOSTIC READ LONG WRITE LONG READ BUFFER WRITE BUFFER IDLE IDLE IMMEDIATE STANDBY STANDBY IMMEDIATE...
5.4 Command Protocol 5.4 Command Protocol The host should confirm that the BSY bit of the Status register of the device is 0 prior to issue a command. If BSY bit is 1, the host should wait for issuing a command until BSY bit is cleared to 0.
Interface words, the host should receive the relevant sector of data (512 bytes of uninsured dummy data) or release the DRQ status by resetting. Figure 5.3 shows an example of READ SECTOR(S) command protocol, and Figure 5.4 shows an example protocol for command abort. Figure 5.3 Read Sector(s) command protocol Note: For transfer of a sector of data, the host needs to read Status register (X’1F7’) in order to...
5.4 Command Protocol last sector in multiple-sector reading. If the timing to read the Status register does not meet above condition, normal data transfer operation is not guaranteed. When the host new command even if the device requests the data transfer (setting in DRQ bit), the correct device operation is not guaranteed.
Interface b) The host writes a command code in the Command register. The drive sets the BSY bit of the Status register. c) When the device is ready to receive the data of the first sector, the device sets DRQ bit and clears BSY bit. d) The host writes one sector of data through the Data register.
5.4 Command Protocol Note: For transfer of a sector of data, the host needs to read Status register (X’1F7’) in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the device to 50 s after the completion of the sector data transfer. Note that the host does not need to read the Status register for the first and the last sector to be transferred.
Interface 5.4.4 Other commands READ MULTIPLE SLEEP WRITE MULTIPLE See the description of each command. 5.4.5 DMA data transfer commands READ DMA WRITE DMA Starting the DMA transfer command is the same as the READ SECTOR(S) or WRITE SECTOR(S) command except the point that the host initializes the DMA channel preceding the command issurance.
Interface 5.5.2 Single word DMA data transfer Figure 5.9 show the single word DMA data transfer timing between the device and the host system. Figure 5.9 Single word DMA data transfer timing (mode 2) 5-78 C141-E042-01EN...
5.5 Timing 5.5.3 Multiword DMA data transfer Figure 5.10 shows the multiword DMA data transfer timing between the device and the host system. Figure 5.10 Multiword DMA data transfer timing (mode 2) 5.5.4 Power-on and reset Figure 5.11 shows power-on and reset (hardware and software reset) timing. (1) Only master device is present C141-E042-01EN 5-79...
Operations 6.1 Device Response to the Reset This section describes how the PDIAG- and DASP- signals responds when the power of the IDD is turned on or the IDD receives a reset or diagnostic command. 6.1.1 Response to power-on After the master device (device 0) releases its own power-on reset state, the master device shall check a DASP- signal for up to 450 ms to confirm presence of a slave device (device 1).
Operations 6.1.2 Response to hardware reset Response to RESET- (hardware reset through the interface) is similar to the power-on reset. Upon receipt of hardware reset, the master device checks a DASP- signal for up to 450 ms to confirm presence of a slave device. The master device recognizes the presence of the slave device when it confirms assertion of the DASP- signal.
6.1 Device Response to the Reset 6.1.3 Response to software reset The master device does not check the DASP- signal for a software reset. If a slave device is present, the master device checks the PDIAG- signal for up to 15 seconds to see if the slave device has completed the self-diagnosis successfully.
Operations 6.1.4 Response to diagnostic command When the master device receives an EXECUTE DEVICE DIAGNOSTIC command and the slave device is present, the master device checks the PDIAG- signal for up to 6 seconds to see if the slave device has completed the self- diagnosis successfully.
6.2 Address Translation 6.2 Address Translation When the IDD receives any command which involves access to the disk medium, the IDD always implements the address translation from the logical address (a host-specified address) to the physical address (logical to physical address translation).
Operations 6.2.2 Logical address (1) CHS mode Logical address assignment starts from physical cylinder (PC) 0, physical head (PH) 0, and physical sector (PS) 1 and is assigned by calculating the number of sectors per track that is specified by the INITIALIZE DEVICE PARAMETERS command.
6.3 Power Save (2) LBA mode Logical address assignment in the LBA mode starts from physical cylinder 0, physical head 0, and physical sector 1. If the last sector in a zone of a physical head is used, the track is switched and the next LBA is assigned to the initial sector in the same zone of the subsequent physical head.
Operations Standby mode Sleep mode The drive moves from the Active mode to the idle mode by itself. Regardless of whether the power down is enabled, the device enters the idle mode. The device also enters the idle mode in the same way after power-on sequence is completed.
6.4 Defect Management When one of following commands is issued, the command is executed normally and the device is still stayed in the standby mode. Reset (hardware or software) STANDBY command STANDBY IMMEDIATE command INITIALIZE DEVICE PARAMETERS command CHECK POWER MODE command (4) Sleep mode The power consumption of the drive is minimal in this mode.
Operations 6.4.1 Spare area Following two types of spare area are provided for every physical head. 1) Spare cylinder for sector slip: used for alternating defective sectors at formatting in shipment (4 cylinders) 2) Spare cylinder for alternative assignment: used for automatic alternative assignment at read error occurrence. (2 cylinders) 6.4.2 Alternating defective sectors The two alternating methods described below are available:...
6.4 Defect Management (2) Alternate cylinder assignment A defective sector is assigned to the spare sector in the alternate cylinder. This processing is performed when the alternate assignment is specified in the FORMAT TRACK command or when the automatic alternate processing is performed at read error occurrence.
Operations 6.5 Read-Ahead Cache After read command which involes read data from the disk medium is completed, the read-ahead cache function reads the subsequent data blocks automatically and stores the data to the data buffer. When the next command requests to read the read-ahead data, the data can be transferred from the data buffer without accessing the disk medium.
6.5 Read-Ahead Cache READ SECTOR (S) READ MULTIPLE READ DMA When caching operation is disabled by the SET FEATURES command, no caching operation is performed. (2) Data that are object of caching operation Follow data are object of caching operation. 1) Read-ahead data read from the medium to the data buffer after completion of the command that are object of caching operation.
Operations READ MULTIPLE WRITE SECTOR(S) WRITE MULTIPLE WRITE VERIFY SECTOR(S) 3) Caching operation is inhibited by the SET FEATURES command. 4) Issued command is terminated with an error. 5) Soft reset or hard reset occurs, or power is turned off. 6) The device enters the sleep mode.
6.5 Read-Ahead Cache 2) Transfers the requested data that already read to the host system with reading the requested data from the disk media. Stores the read-requested data upto this point Empty area Read-requested data 3) After reading the requested data and transferring the requested data to the host system had been completed, the disk drive stops command execution without performing the read-ahead operation.
Operations 1) At receiving the sequential read command, the disk drive sets the DAP and HAP to the start address of the segment and reads the requested data from the load of the segment. Mis-hit data Empty area 2) The disk drive transfers the requested data that is already read to the host system with reading the requested data.
6.5 Read-Ahead Cache Sequential hit When the previously executed read command is the sequential command and the last sector address of the previous read command is sequential to the lead sector address of the received read command, the disk drive transfers the hit data in the buffer to the host system.
Operations 4) Finally, the cache data in the buffer is as follows. Read-ahead data Start LBA Last LBA (3) Full hit (hit all) All requested data are stored in the data buffer. The disk drive starts transferring the requested data from the address of which the requested data is stored. After completion of command, a previously existed cache data before the full hit reading are still kept in the buffer, and the disk drive does not perform the read- ahead operation.
6.5 Read-Ahead Cache (4) Partially hit A part of requested data including a lead sector are stored in the data buffer. The disk drive starts the data transfer from the address of the hit data corresponding to the lead sector of the requested data, and reads remaining requested data from the disk media directly.
Operations 6.6 Write Cache The write cache function of the drive makes a high speed processing in the case that data to be written by a write command is physically sequent the data of previous command and random write operation is performed. When the drive receives a write command, the drive starts transferring data of sectors requested by the host system and writing on the disk medium.
Glossary Actuator Head positioning assembly. The actuator consists of a voice coil motor and head arm. If positions the read-write (R-W) head. AT bus A bus between the host CPU and adapter board ATA (AT Attachment) standard The ATA standard is for a PC AT interface regulated to establish compatibility between products manufactured by different vendors.
Glossary MTBF Mean time between failures. The MTBF is calculated by dividing the total operation time (total power-on time) by the number of failures in the disk drive during operation. MTTR Mean time to repair. The MTTR is the average time required for a service person to diagnose and repair a faulty drive.
Glossary Status The status is a piece of one-byte information posted from the drive to the host when command execution is ended. The status indicates the command termination state. Voice coil motor. The voice coil motor is excited by one or more magnets. In this drive, the VCM is used to position the heads accurately and quickly.
Acronyms and Abbreviations Hard disk drive ABRT Abored command Automatic idle control IDNF ID not found AMNF Address mark not found IRQ14 Interrupt request 14 AT attachment American wire gage Light emitting diode Bad block detected BIOS Basic input-output system Mega-byte MB/S Mega-byte per seconds...
Index Command, sequential 6-17 Data, object of caching operation 6-15 Command, without data transfer 5-73 Data area 4-18 Command block register 5-8 Data assurance in event of power failure Command code 5-14, 5-67 Command description 5-16 Data buffer 1-3 Command processing 4-9 Data buffer configuration 6-14 Command protocol 5-69 Data corruption 3-6...
Index Mis-hit 6-16 Physical interface 5-2 Mode, acceleration 4-21 PIO data transfer 5-76 Mode, active 6-10 PIO Mode 4 2-4 Mode, CHS 6-8 Positioning error 1-9 Mode, idle 6-10 Power amplifier 4-17 Mode, LBA 6-9 Power commands 6-11 Mode, power save 1-2, 6-9 Power dissipation 1-6 Mode, sleep 6-11 Power-on 5-79...
Index Read/write preamplifier 4-9 Servo control circuit 4-14 RECALIBRATE 5-28 Servo D 4-19 Recovery, write/read 4-19 Servo format, data-surface 4-18 Register, command block 5-8 Servo frame format 4-18 Register, control block 5-13 Servo mark 4-19 Register, I/O 5-6 SET FEATURES 5-38 Reliability 1-8 SET MULTIPLE MODE 5-40 Requirement, power 1-5...
Index Surface temperature measurement point Translation, address 6-7, 6-8 System configuration 2-4 Unrecoverable read error 1-9 Usage of read segment 6-16 User password 5-66 Temperature, ambient 3-5 Temperature, range 1-2 Temperature measurement point, surface VCM 4-3 VCM current sense resistor (CSR) 4-17 Temperature range 1-2 Vibration 1-8 Theory of device operation 4-1...
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