Intel 5148LV - Xeon Dual Core Active H Datasheet page 71

Signal Definitions
Table 5-1. Signal Definitions (Sheet 7 of 7)
Name Type
TMS I
TRDY# I
TRST# I
V I
CCPLL
VCC_DIE_SENSE O
VCC_DIE_SENSE2
VID[6:1] O
VID_SELECT O
VSS_DIE_SENSE O
VSS_DIE_SENSE2
VTT P
VTT_OUT O
VTT_SEL O
Notes:
1. For this processor land on the Dual-Core Intel
one. Maximum number of priority agents is zero.
2. For this processor land on the Dual-Core Intel
two. Maximum number of priority agents is zero.
3. For this processor land on the Dual-Core Intel
two. Maximum number of priority agents is one.
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Dual-Core Intel Xeon Processor 5100 Series Datasheet
TMS (Test Mode Select) is a JTAG specification support signal used by debug tools.
TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a
write or implicit writeback data transfer. TRDY# must connect the appropriate pins of
all FSB agents.
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low
during power on Reset.
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The Dual-Core Intel Xeon Processor 5100 Series implements an on-die PLL filter
solution. The V input is used as a PLL supply voltage.
CCPLL
VCC_DIE_SENSE and VCC_DIE_SENSE2 provides an isolated, low impedance
connection to the processor core power and ground. This signal should be connected
to the voltage regulator feedback signal, which insures the output voltage (that is,
processor voltage) remains within specification. Please see the applicable platform
design guide for implementation details.
VID[6:1] (Voltage ID) pins are used to support automatic selection of power supply
voltages (V ). These are CMOS signals that are driven by the processor and must be
CC
pulled up through a resistor. Conversely, the voltage regulator output must be
disabled prior to the voltage supply for these pins becomes invalid. The VID pins are
needed to support processor voltage specification variations. See
definitions of these pins. The VR must supply the voltage that is requested by these
pins, or disable itself.
VID_SELECT is an output from the processor which selects the appropriate VID table
for the Voltage Regulator. This signal is not connected to the processor die. This signal
is a no-connect on the Dual-Core Intel
VSS_DIE_SENSE and VSS_DIE_SENSE2 provides an isolated, low impedance
connection to the processor core power and ground. This signal should be connected
to the voltage regulator feedback signal, which insures the output voltage (that is,
processor voltage) remains within specification. Please see the applicable platform
design guide for implementation details.
The FSB termination voltage input pins. Refer to
The VTT_OUT signals are included in order to provide a local V
require termination to V on the motherboard.
TT
The VTT_SEL signal is used to select the correct V
VTT_SEL is a no-connect on the Dual-Core Intel
package.
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Xeon Processor 5100 Series , the maximum number of symmetric agents is
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Xeon Processor 5100 Series , the maximum number of symmetric agents is
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Xeon Processor 5100 Series , the maximum number of symmetric agents is
Description
Table 2-3
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Xeon Processor 5100 Series package.
Table 2-13 for further details.
for some signals that
TT
voltage level for the processor.
TT
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Xeon Processor 5100 Series
§
Notes
for
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