Intel 5148LV - Xeon Dual Core Active H Datasheet page 70

Table 5-1. Signal Definitions (Sheet 6 of 7)
Name Type
REQ[4:0]# I/O
RESET# I
RS[2:0]# I
RSP# I
SKTOCC# O
SMI# I
STPCLK# I
TCK I
TDI I
TDO O
TESTHI[11:0]
I
THERMTRIP# O
70
REQ[4:0]# (Request Command) must connect the appropriate pins of all processor
FSB agents. They are asserted by the current bus owner to define the currently active
transaction type. These signals are source synchronous to ADSTB[1:0]#. Refer to the
AP[1:0]# signal description for details on parity checking of these signals.
Asserting the RESET# signal resets all processors to known states and invalidates
their internal caches without writing back any of their contents. For a power-on Reset,
RESET# must stay active for at least 1 ms after V
proper specifications. On observing active RESET#, all FSB agents will deassert their
outputs within two clocks. RESET# must not be kept asserted for more than 10 ms
while PWRGOOD is asserted.
A number of bus signals are sampled at the active-to-inactive transition of RESET#
for power-on configuration. These configuration options are described in the
Section 7.1.
This signal does not have on-die termination and must be terminated on the system
board.
RS[2:0]# (Response Status) are driven by the response agent (the agent responsible
for completion of the current transaction), and must connect the appropriate pins of
all processor FSB agents.
RSP# (Response Parity) is driven by the response agent (the agent responsible for
completion of the current transaction) during assertion of RS[2:0]#, the signals for
which RSP# provides parity protection. It must connect to the appropriate pins of all
processor FSB agents.
A correct parity signal is high if an even number of covered signals are low and low if
an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also high,
since this indicates it is not being driven by any agent guaranteeing correct parity.
SKTOCC# (Socket occupied) will be pulled to ground by the processor to indicate that
the processor is present. There is no connection to the processor silicon for this
signal.
SMI# (System Management Interrupt) is asserted asynchronously by system logic.
On accepting a System Management Interrupt, processors save the current state and
enter System Management Mode (SMM). An SMI Acknowledge transaction is issued,
and the processor begins program execution from the SMM handler.
If SMI# is asserted during the deassertion of RESET# the processor will tri-state its
outputs. See Section 7.1.
STPCLK# (Stop Clock), when asserted, causes processors to enter a low power Stop-
Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops
providing internal clock signals to all processor core units except the FSB and APIC
units. The processor continues to snoop bus transactions and service interrupts while
in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal
clock to all units and resumes execution. The assertion of STPCLK# has no effect on
the bus clock; STPCLK# is an asynchronous input.
TCK (Test Clock) provides the clock input for the processor Test Bus (also known as
the Test Access Port).
TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial
input needed for JTAG specification support.
TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the
serial output needed for JTAG specification support.
TESTHI[11:0] must be connected to a V
processor operation. Refer to
Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction
temperature has reached a temperature beyond which permanent silicon damage
may occur. Measurement of the temperature is accomplished through an internal
thermal sensor. Upon assertion of THERMTRIP#, the processor will shut off its internal
clocks (thus halting program execution) in an attempt to reduce the processor
junction temperature. To protect the processor its core voltage (V
removed following the assertion of THERMTRIP#. Intel also recommends the removal
of V when THERMTRIP# is asserted.
TT
Driving of the THERMTRIP# signals is enabled within 10 μs of the assertion of
PWRGOOD and is disabled on de-assertion of PWRGOOD. Once activated,
THERMTRIP# remains latched until PWRGOOD is de-asserted. While the de-assertion
of the PWRGOOD signal will de-assert THERMTRIP#, if the processor's junction
temperature remains at or above the trip level, THERMTRIP# will again be asserted
within 10 μs of the assertion of PWRGOOD.
Description
and BCLK have reached their
CC
power source through a resistor for proper
TT
Section 2.6 for TESTHI restrictions.
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Dual-Core Intel Xeon
Signal Definitions
Notes
3
3
3
3
2
2
1
) must be
CC
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Processor 5100 Series Datasheet