Fluke 5790A Service Manual page 62

5790A
Service Manual
receiver on the Digital Motherboard. Another fiber-optic cable links the other
receiver/transmitter pair on the motherboards.
2-72. Interface to Guarded Digital Bus
The interface to the guarded digital bus consists of a 74HCT245 (U55), a 74HCT244
(U52), a 74HC137 (U53), resistor packs Z52, Z53, and Z54, and the POP line from U58.
U52A and U52B buffer various control and address lines. Resistors from Z52 pull the
lines of U52A to the desired inactive states when BUSEN* is at a logic high, disabling
the bus. U55 is a bi-directional data bus buffer (D0-D7). Resistor packs Z53 and Z54
match the lines of the buffered data bus, reducing reflected noise. IC U53 performs a 3-
to-8 decode of the address lines AB3-AB5, generating 8 select lines (CS0*-CS7*) on the
guarded digital bus. These 8 signals select the various components on the Analog
Motherboard. The POP signal from U58 is a reset line sent to the analog assemblies.
DUART (dual asynchronous receiver transmitter) U65 provides the serial communication
channel to the A/D chip on the A/D Amplifier (A15) Assembly. HGRCV and HGXMT
are the serial communication lines from and to the A/D chip.
2-73. Inguard CPU Interrupts
The Inguard CPU microprocessor handles many different interrupts. These are listed in
Table 2-12 in order of priority with the highest priority interrupts first.
Vector
MSB LSB
FFFE FFFF
FFEE FFEF
FFFC FFFD
FFFA FFFB
FFF8 FFF9
FFF6 FFF7
FFF4 FFF5
FFF2 FFF3
FFEC FFED
FFEA FFEB
FFF0 FFF1
RDRF = Receive Data Register Full
ORFE = Overrun Framing Error
TDRE = Transmit Data Registry Empty
PER = Parity Error
2-32
Table 2-12. Inguard CPU Interrupts
Interrupt
RES* Power up and Reset
TRAP Address error or opcode error
NMI* Nonmaskable interrupt (Watching NMIPOP*)
SWI Software interrupt (unused)
IRQ1* DUART (IRQ1*)
ICI Timer 1 input capture (unused)
OCI Timer 1 output capture 1,2 (software timers)
TOI Timer 1 overflow (unused)
CMI Timer 2 counter match (unused)
IRQ2* Input protection fault (IRQ2*)
SIO RDRF ORFE
Description
TDRE PER (internal UART)